From: James Hogan Date: Thu, 26 Jun 2014 09:44:22 +0000 (+0100) Subject: mips/kvm: Init EBase to correct KSEG0 X-Git-Tag: qemu-xen-4.6.0-rc1~316^2~9 X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=0a2672b7ead72b7c788200499a63a4d5f2faa74a;p=qemu-upstream-4.6-testing.git mips/kvm: Init EBase to correct KSEG0 The EBase CP0 register is initialised to 0x80000000, however with KVM the guest's KSEG0 is at 0x40000000. The incorrect value doesn't get passed to KVM yet as KVM doesn't implement the EBase register, however we should set it correctly now so as not to break migration/loadvm to a future version of QEMU that does support EBase. Cc: Aurelien Jarno Cc: Paolo Bonzini Signed-off-by: James Hogan Reviewed-by: Aurelien Jarno Signed-off-by: Paolo Bonzini --- diff --git a/target-mips/translate.c b/target-mips/translate.c index 2f91959ed..d7b8c4dbc 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -28,6 +28,7 @@ #include "exec/helper-proto.h" #include "exec/helper-gen.h" +#include "sysemu/kvm.h" #define MIPS_DEBUG_DISAS 0 //#define MIPS_DEBUG_SIGN_EXTENSIONS @@ -16076,7 +16077,12 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_Random = env->tlb->nb_tlb - 1; env->tlb->tlb_in_use = env->tlb->nb_tlb; env->CP0_Wired = 0; - env->CP0_EBase = 0x80000000 | (cs->cpu_index & 0x3FF); + env->CP0_EBase = (cs->cpu_index & 0x3FF); + if (kvm_enabled()) { + env->CP0_EBase |= 0x40000000; + } else { + env->CP0_EBase |= 0x80000000; + } env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); /* vectored interrupts not implemented, timer on int 7, no performance counters. */