From: Andrew Cooper <andrew.cooper3@citrix.com>
Date: Sun, 29 Dec 2024 14:06:18 +0000 (+0000)
Subject: x86/elf: Improve code generation in elf_core_save_regs()
X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=0754534b8a381444e209bb91a6b4c6fc325ac04e;p=people%2Fandrewcoop%2Fxen.git

x86/elf: Improve code generation in elf_core_save_regs()

A CALL with 0 displacement is handled specially, and is why this logic
functions even with CET Shadow Stacks active.  Nevertheless a RIP-relative LEA
is the more normal way of doing this in 64bit code.

The retrieval of flags modifies the stack pointer so needs to state a
dependency on the stack pointer.  Despite it's name, ASM_CALL_CONSTRAINT is
the way to do this.

read_sreg() forces the answer through a register, causing code generation of
the form:

    mov    %gs, %eax
    mov    %eax, %eax
    mov    %rax, 0x140(%rsi)

Encode the reads directly with a memory operand.  This results in a 16bit
store instead of an 64bit store, but the backing memory is zeroed.

While cleaning this up, drop one piece of trailing whitespace.

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
---

diff --git a/xen/arch/x86/include/asm/x86_64/elf.h b/xen/arch/x86/include/asm/x86_64/elf.h
index 00227e0e12..f33be46dde 100644
--- a/xen/arch/x86/include/asm/x86_64/elf.h
+++ b/xen/arch/x86/include/asm/x86_64/elf.h
@@ -34,7 +34,7 @@ typedef struct {
     unsigned long gs;
 } ELF_Gregset;
 
-static inline void elf_core_save_regs(ELF_Gregset *core_regs, 
+static inline void elf_core_save_regs(ELF_Gregset *core_regs,
                                       crash_xen_core_t *xen_core_regs)
 {
     asm ( "movq %%r15, %0" : "=m" (core_regs->r15) );
@@ -54,17 +54,17 @@ static inline void elf_core_save_regs(ELF_Gregset *core_regs,
     asm ( "movq %%rdi, %0" : "=m" (core_regs->rdi) );
 
     /* orig_rax not filled in for now */
-    asm ( "call 0f; 0: popq %0" : "=m" (core_regs->rip) );
-    core_regs->cs = read_sreg(cs);
-    asm ( "pushfq; popq %0" : "=m" (core_regs->rflags) );
+    asm ( "lea (%%rip), %0" : "=r" (core_regs->rip) );
+    asm ( "mov %%cs, %0" : "=m" (core_regs->cs) );
+    asm ( "pushfq; popq %0" : "=m" (core_regs->rflags) ASM_CALL_CONSTRAINT );
     asm ( "movq %%rsp, %0" : "=m" (core_regs->rsp) );
-    core_regs->ss = read_sreg(ss);
+    asm ( "mov %%ss, %0" : "=m" (core_regs->ss) );
     rdmsrl(MSR_FS_BASE, core_regs->thread_fs);
     rdmsrl(MSR_GS_BASE, core_regs->thread_gs);
-    core_regs->ds = read_sreg(ds);
-    core_regs->es = read_sreg(es);
-    core_regs->fs = read_sreg(fs);
-    core_regs->gs = read_sreg(gs);
+    asm ( "mov %%ds, %0" : "=m" (core_regs->ds) );
+    asm ( "mov %%es, %0" : "=m" (core_regs->es) );
+    asm ( "mov %%fs, %0" : "=m" (core_regs->fs) );
+    asm ( "mov %%gs, %0" : "=m" (core_regs->gs) );
 
     asm ( "mov %%cr0, %0" : "=r" (xen_core_regs->cr0) );
     asm ( "mov %%cr2, %0" : "=r" (xen_core_regs->cr2) );