From: Andrew Cooper Date: Mon, 19 Feb 2018 13:35:58 +0000 (+0000) Subject: x86/pv: Expose RDTSCP to PV guests X-Git-Url: http://xenbits.xensource.com/gitweb?a=commitdiff_plain;h=068118aaba842af21f0b1025925e3a2e04808c1f;p=people%2Fsstabellini%2Fxen-unstable.git%2F.git x86/pv: Expose RDTSCP to PV guests The final remnanat of PVRDTSCP is that we would emulate RDTSCP even on hardware which lacked the instruction. RDTSCP is available on almost all 64-bit x86 hardware. Remove this emulation, drop the TSC_MODE_PVRDTSCP constant, and allow RDTSCP in a PV guest's CPUID policy. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- diff --git a/xen/arch/x86/pv/emul-inv-op.c b/xen/arch/x86/pv/emul-inv-op.c index 56f5a45b68..91d05790c2 100644 --- a/xen/arch/x86/pv/emul-inv-op.c +++ b/xen/arch/x86/pv/emul-inv-op.c @@ -41,31 +41,6 @@ #include "emulate.h" -static int emulate_invalid_rdtscp(struct cpu_user_regs *regs) -{ - char opcode[3]; - unsigned long eip, rc; - struct vcpu *v = current; - const struct domain *currd = v->domain; - - eip = regs->rip; - if ( (rc = copy_from_user(opcode, (char *)eip, sizeof(opcode))) != 0 ) - { - pv_inject_page_fault(0, eip + sizeof(opcode) - rc); - return EXCRET_fault_fixed; - } - if ( memcmp(opcode, "\xf\x1\xf9", sizeof(opcode)) ) - return 0; - eip += sizeof(opcode); - - msr_split(regs, pv_soft_rdtsc(v, regs)); - regs->rcx = (currd->arch.tsc_mode == TSC_MODE_PVRDTSCP - ? currd->arch.incarnation : 0); - - pv_emul_instruction_done(regs, eip); - return EXCRET_fault_fixed; -} - static int emulate_forced_invalid_op(struct cpu_user_regs *regs) { char sig[5], instr[2]; @@ -121,7 +96,7 @@ static int emulate_forced_invalid_op(struct cpu_user_regs *regs) bool pv_emulate_invalid_op(struct cpu_user_regs *regs) { - return !emulate_invalid_rdtscp(regs) && !emulate_forced_invalid_op(regs); + return !emulate_forced_invalid_op(regs); } /* diff --git a/xen/include/asm-x86/time.h b/xen/include/asm-x86/time.h index 4f3d926884..f347311cc4 100644 --- a/xen/include/asm-x86/time.h +++ b/xen/include/asm-x86/time.h @@ -17,7 +17,6 @@ #define TSC_MODE_DEFAULT 0 #define TSC_MODE_ALWAYS_EMULATE 1 #define TSC_MODE_NEVER_EMULATE 2 -#define TSC_MODE_PVRDTSCP 3 typedef u64 cycles_t; diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 6c82816fd3..fbc68fa29f 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -156,7 +156,7 @@ XEN_CPUFEATURE(NX, 2*32+20) /*A Execute Disable */ XEN_CPUFEATURE(MMXEXT, 2*32+22) /*A AMD MMX extensions */ XEN_CPUFEATURE(FFXSR, 2*32+25) /*A FFXSR instruction optimizations */ XEN_CPUFEATURE(PAGE1GB, 2*32+26) /*H 1Gb large page support */ -XEN_CPUFEATURE(RDTSCP, 2*32+27) /*S RDTSCP */ +XEN_CPUFEATURE(RDTSCP, 2*32+27) /*A RDTSCP */ XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */ XEN_CPUFEATURE(3DNOWEXT, 2*32+30) /*A AMD 3DNow! extensions */ XEN_CPUFEATURE(3DNOW, 2*32+31) /*A 3DNow! */