Convert float move ops to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4090 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-sparc/fop_template.h b/target-sparc/fop_template.h
deleted file mode 100644 (file)
index 0c045b8..0000000
--- a/target-sparc/fop_template.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- *  SPARC micro operations (templates for various register related
- *  operations)
- *
- *  Copyright (c) 2003 Fabrice Bellard
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-/* floating point registers moves */
-void OPPROTO glue(op_load_fpr_FT0_fpr, REGNAME)(void)
-{
-    FT0 = REG;
-}
-
-void OPPROTO glue(op_store_FT0_fpr_fpr, REGNAME)(void)
-{
-    REG = FT0;
-}
-
-void OPPROTO glue(op_load_fpr_FT1_fpr, REGNAME)(void)
-{
-    FT1 = REG;
-}
-
-void OPPROTO glue(op_store_FT1_fpr_fpr, REGNAME)(void)
-{
-    REG = FT1;
-}
-
-/* double floating point registers moves */
-void OPPROTO glue(op_load_fpr_DT0_fpr, REGNAME)(void)
-{
-    CPU_DoubleU u;
-    uint32_t *p = (uint32_t *)®
-    u.l.lower = *(p +1);
-    u.l.upper = *p;
-    DT0 = u.d;
-}
-
-void OPPROTO glue(op_store_DT0_fpr_fpr, REGNAME)(void)
-{
-    CPU_DoubleU u;
-    uint32_t *p = (uint32_t *)®
-    u.d = DT0;
-    *(p +1) = u.l.lower;
-    *p = u.l.upper;
-}
-
-void OPPROTO glue(op_load_fpr_DT1_fpr, REGNAME)(void)
-{
-    CPU_DoubleU u;
-    uint32_t *p = (uint32_t *)®
-    u.l.lower = *(p +1);
-    u.l.upper = *p;
-    DT1 = u.d;
-}
-
-void OPPROTO glue(op_store_DT1_fpr_fpr, REGNAME)(void)
-{
-    CPU_DoubleU u;
-    uint32_t *p = (uint32_t *)®
-    u.d = DT1;
-    *(p +1) = u.l.lower;
-    *p = u.l.upper;
-}
-
-#if defined(CONFIG_USER_ONLY)
-/* quad floating point registers moves */
-void OPPROTO glue(op_load_fpr_QT0_fpr, REGNAME)(void)
-{
-    CPU_QuadU u;
-    uint32_t *p = (uint32_t *)®
-    u.l.lowest = *(p + 3);
-    u.l.lower = *(p + 2);
-    u.l.upper = *(p + 1);
-    u.l.upmost = *p;
-    QT0 = u.q;
-}
-
-void OPPROTO glue(op_store_QT0_fpr_fpr, REGNAME)(void)
-{
-    CPU_QuadU u;
-    uint32_t *p = (uint32_t *)®
-    u.q = QT0;
-    *(p + 3) = u.l.lowest;
-    *(p + 2) = u.l.lower;
-    *(p + 1) = u.l.upper;
-    *p = u.l.upmost;
-}
-
-void OPPROTO glue(op_load_fpr_QT1_fpr, REGNAME)(void)
-{
-    CPU_QuadU u;
-    uint32_t *p = (uint32_t *)®
-    u.l.lowest = *(p + 3);
-    u.l.lower = *(p + 2);
-    u.l.upper = *(p + 1);
-    u.l.upmost = *p;
-    QT1 = u.q;
-}
-
-void OPPROTO glue(op_store_QT1_fpr_fpr, REGNAME)(void)
-{
-    CPU_QuadU u;
-    uint32_t *p = (uint32_t *)®
-    u.q = QT1;
-    *(p + 3) = u.l.lowest;
-    *(p + 2) = u.l.lower;
-    *(p + 1) = u.l.upper;
-    *p = u.l.upmost;
-}
-#endif
-
-#undef REG
-#undef REGNAME

diff --git a/target-sparc/op.c b/target-sparc/op.c
index 3bd8d484edd81adde08f09bce2abcb258a271ee8..cf614cfbfa325b2e951e6a912fb0f5d9c15f0ba4 100644 (file)
--- a/target-sparc/op.c
+++ b/target-sparc/op.c
@@ -21,154 +21,6 @@
 #include "exec.h"
 #include "helper.h"
 
-#define REGNAME f0
-#define REG (env->fpr[0])
-#include "fop_template.h"
-#define REGNAME f1
-#define REG (env->fpr[1])
-#include "fop_template.h"
-#define REGNAME f2
-#define REG (env->fpr[2])
-#include "fop_template.h"
-#define REGNAME f3
-#define REG (env->fpr[3])
-#include "fop_template.h"
-#define REGNAME f4
-#define REG (env->fpr[4])
-#include "fop_template.h"
-#define REGNAME f5
-#define REG (env->fpr[5])
-#include "fop_template.h"
-#define REGNAME f6
-#define REG (env->fpr[6])
-#include "fop_template.h"
-#define REGNAME f7
-#define REG (env->fpr[7])
-#include "fop_template.h"
-#define REGNAME f8
-#define REG (env->fpr[8])
-#include "fop_template.h"
-#define REGNAME f9
-#define REG (env->fpr[9])
-#include "fop_template.h"
-#define REGNAME f10
-#define REG (env->fpr[10])
-#include "fop_template.h"
-#define REGNAME f11
-#define REG (env->fpr[11])
-#include "fop_template.h"
-#define REGNAME f12
-#define REG (env->fpr[12])
-#include "fop_template.h"
-#define REGNAME f13
-#define REG (env->fpr[13])
-#include "fop_template.h"
-#define REGNAME f14
-#define REG (env->fpr[14])
-#include "fop_template.h"
-#define REGNAME f15
-#define REG (env->fpr[15])
-#include "fop_template.h"
-#define REGNAME f16
-#define REG (env->fpr[16])
-#include "fop_template.h"
-#define REGNAME f17
-#define REG (env->fpr[17])
-#include "fop_template.h"
-#define REGNAME f18
-#define REG (env->fpr[18])
-#include "fop_template.h"
-#define REGNAME f19
-#define REG (env->fpr[19])
-#include "fop_template.h"
-#define REGNAME f20
-#define REG (env->fpr[20])
-#include "fop_template.h"
-#define REGNAME f21
-#define REG (env->fpr[21])
-#include "fop_template.h"
-#define REGNAME f22
-#define REG (env->fpr[22])
-#include "fop_template.h"
-#define REGNAME f23
-#define REG (env->fpr[23])
-#include "fop_template.h"
-#define REGNAME f24
-#define REG (env->fpr[24])
-#include "fop_template.h"
-#define REGNAME f25
-#define REG (env->fpr[25])
-#include "fop_template.h"
-#define REGNAME f26
-#define REG (env->fpr[26])
-#include "fop_template.h"
-#define REGNAME f27
-#define REG (env->fpr[27])
-#include "fop_template.h"
-#define REGNAME f28
-#define REG (env->fpr[28])
-#include "fop_template.h"
-#define REGNAME f29
-#define REG (env->fpr[29])
-#include "fop_template.h"
-#define REGNAME f30
-#define REG (env->fpr[30])
-#include "fop_template.h"
-#define REGNAME f31
-#define REG (env->fpr[31])
-#include "fop_template.h"
-
-#ifdef TARGET_SPARC64
-#define REGNAME f32
-#define REG (env->fpr[32])
-#include "fop_template.h"
-#define REGNAME f34
-#define REG (env->fpr[34])
-#include "fop_template.h"
-#define REGNAME f36
-#define REG (env->fpr[36])
-#include "fop_template.h"
-#define REGNAME f38
-#define REG (env->fpr[38])
-#include "fop_template.h"
-#define REGNAME f40
-#define REG (env->fpr[40])
-#include "fop_template.h"
-#define REGNAME f42
-#define REG (env->fpr[42])
-#include "fop_template.h"
-#define REGNAME f44
-#define REG (env->fpr[44])
-#include "fop_template.h"
-#define REGNAME f46
-#define REG (env->fpr[46])
-#include "fop_template.h"
-#define REGNAME f48
-#define REG (env->fpr[47])
-#include "fop_template.h"
-#define REGNAME f50
-#define REG (env->fpr[50])
-#include "fop_template.h"
-#define REGNAME f52
-#define REG (env->fpr[52])
-#include "fop_template.h"
-#define REGNAME f54
-#define REG (env->fpr[54])
-#include "fop_template.h"
-#define REGNAME f56
-#define REG (env->fpr[56])
-#include "fop_template.h"
-#define REGNAME f58
-#define REG (env->fpr[58])
-#include "fop_template.h"
-#define REGNAME f60
-#define REG (env->fpr[60])
-#include "fop_template.h"
-#define REGNAME f62
-#define REG (env->fpr[62])
-#include "fop_template.h"
-#endif
-
 /* Load and store */
 #define MEMSUFFIX _raw
 #include "op_mem.h"

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 1ab4d7e9569d5bac76636f566d0c37b23fad250f..52119a312da855b9184520629c7b7b8c3727fca0 100644 (file)
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -114,60 +114,85 @@ static int sign_extend(int x, int len)
 
 static void disas_sparc_insn(DisasContext * dc);
 
-#ifdef TARGET_SPARC64
-#define GEN32(func, NAME) \
-static GenOpFunc * const NAME ## _table [64] = {                              \
-NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
-NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
-NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
-NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
-NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
-NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
-NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
-NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
-NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0,                   \
-NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0,                   \
-NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0,                   \
-NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0,                   \
-};                                                                            \
-static inline void func(int n)                                                \
-{                                                                             \
-    NAME ## _table[n]();                                                      \
+/* floating point registers moves */
+static void gen_op_load_fpr_FT0(unsigned int src)
+{
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0));
 }
-#else
-#define GEN32(func, NAME) \
-static GenOpFunc *const NAME ## _table [32] = {                               \
-NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
-NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
-NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
-NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
-NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
-NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
-NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
-NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
-};                                                                            \
-static inline void func(int n)                                                \
-{                                                                             \
-    NAME ## _table[n]();                                                      \
+
+static void gen_op_load_fpr_FT1(unsigned int src)
+{
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft1));
 }
-#endif
 
-/* floating point registers moves */
-GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
-GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
-GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
-GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
+static void gen_op_store_FT0_fpr(unsigned int dst)
+{
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
+}
 
-GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
-GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
-GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
-GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
+static void gen_op_load_fpr_DT0(unsigned int src)
+{
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
+}
 
-#if defined(CONFIG_USER_ONLY)
-GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);
-GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);
-GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);
-GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
+static void gen_op_load_fpr_DT1(unsigned int src)
+{
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
+}
+
+static void gen_op_store_DT0_fpr(unsigned int dst)
+{
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
+}
+
+#ifdef CONFIG_USER_ONLY
+static void gen_op_load_fpr_QT0(unsigned int src)
+{
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
+}
+
+static void gen_op_load_fpr_QT1(unsigned int src)
+{
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
+}
+
+static void gen_op_store_QT0_fpr(unsigned int dst)
+{
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
+    tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
+    tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
+}
 #endif
 
 /* moves */