]> xenbits.xensource.com Git - people/dwmw2/xen.git/commitdiff
x86/spec-ctrl: Misc non-functional cleanup
authorAndrew Cooper <andrew.cooper3@citrix.com>
Wed, 12 Sep 2018 13:36:00 +0000 (14:36 +0100)
committerAndrew Cooper <andrew.cooper3@citrix.com>
Tue, 14 May 2019 14:30:35 +0000 (15:30 +0100)
 * Identify BTI in the spec_ctrl_{enter,exit}_idle() comments, as other
   mitigations will shortly appear.
 * Use alternative_input() and cover the lack of memory cobber with a further
   barrier.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
(cherry picked from commit 9b62eba6c429c327e1507816bef403ccc87357ae)

xen/include/asm-x86/spec_ctrl.h

index 779da2b14d96af55b6e474fe7c9043c56c778fac..20ee11286d146760a09ce7453ffc95c4476e9ef9 100644 (file)
@@ -68,6 +68,8 @@ static always_inline void spec_ctrl_enter_idle(struct cpu_info *info)
     uint32_t val = 0;
 
     /*
+     * Branch Target Injection:
+     *
      * Latch the new shadow value, then enable shadowing, then update the MSR.
      * There are no SMP issues here; only local processor ordering concerns.
      */
@@ -75,8 +77,9 @@ static always_inline void spec_ctrl_enter_idle(struct cpu_info *info)
     barrier();
     info->spec_ctrl_flags |= SCF_use_shadow;
     barrier();
-    asm volatile ( ALTERNATIVE("", "wrmsr", X86_FEATURE_SC_MSR_IDLE)
-                   :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0) : "memory" );
+    alternative_input("", "wrmsr", X86_FEATURE_SC_MSR_IDLE,
+                      "a" (val), "c" (MSR_SPEC_CTRL), "d" (0));
+    barrier();
 }
 
 /* WARNING! `ret`, `call *`, `jmp *` not safe before this call. */
@@ -85,13 +88,16 @@ static always_inline void spec_ctrl_exit_idle(struct cpu_info *info)
     uint32_t val = info->xen_spec_ctrl;
 
     /*
+     * Branch Target Injection:
+     *
      * Disable shadowing before updating the MSR.  There are no SMP issues
      * here; only local processor ordering concerns.
      */
     info->spec_ctrl_flags &= ~SCF_use_shadow;
     barrier();
-    asm volatile ( ALTERNATIVE("", "wrmsr", X86_FEATURE_SC_MSR_IDLE)
-                   :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0) : "memory" );
+    alternative_input("", "wrmsr", X86_FEATURE_SC_MSR_IDLE,
+                      "a" (val), "c" (MSR_SPEC_CTRL), "d" (0));
+    barrier();
 }
 
 #endif /* __ASSEMBLY__ */