xen/arm64: Add missing synchronization barrier in invalidate_cache

The invalidation of the instructions cache requires barriers to ensure
the completion of the invalidation before continuing (see B2.3.4 in ARM
DDI 0487A.j).

This was overlooked in commit fb9d877 "xen/arm64: Add an helper to
invalidate all instruction caches".

Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>

diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
index 79ef7bddb5a9581fb7faaccd7a904d80090825cb..23d778154d280937ae85a1d882bb434fc42212cd 100644 (file)
--- a/xen/include/asm-arm/arm64/page.h
+++ b/xen/include/asm-arm/arm64/page.h
@@ -33,6 +33,8 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
 static inline void invalidate_icache(void)
 {
     asm volatile ("ic ialluis");
+    dsb(ish);               /* Ensure completion of the flush I-cache */
+    isb();
 }
 
 /*