#include <asm/gic.h>
#include <asm/vgic.h>
-#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1))
+#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_get_nr_lrs()) - 1))
#undef GIC_DEBUG
struct pending_irq *p,
unsigned int lr)
{
- unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
+ unsigned int nr_lrs = gic_get_nr_lrs();
unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask);
struct gic_lr lr_val;
unsigned int priority)
{
int i;
- unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
+ unsigned int nr_lrs = gic_get_nr_lrs();
struct pending_irq *p = irq_to_pending(v, virtual_irq);
ASSERT(spin_is_locked(&v->arch.vgic.lock));
{
int i = 0;
unsigned long flags;
- unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
+ unsigned int nr_lrs = gic_get_nr_lrs();
/* The idle domain has no LRs to be cleared. Since gic_restore_state
* doesn't write any LR registers for the idle domain they could be
struct pending_irq *p, *t, *p_r;
struct list_head *inflight_r;
unsigned long flags;
- unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
+ unsigned int nr_lrs = gic_get_nr_lrs();
int lrs = nr_lrs;
spin_lock_irqsave(&v->arch.vgic.lock, flags);
};
extern const struct gic_hw_operations *gic_hw_ops;
+
+static inline unsigned int gic_get_nr_lrs(void)
+{
+ return gic_hw_ops->info->nr_lrs;
+}
+
void register_gic_ops(const struct gic_hw_operations *ops);
int gic_make_hwdom_dt_node(const struct domain *d,
const struct dt_device_node *gic,