[SVM] handle MC threshold registers for Barcelona

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 96e380a9d6f168b5dab33744afcac874752323a6..5dc570dee85deaf871e756f2c6f6e9cf678ffb9c 100644 (file)
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -133,6 +133,7 @@ static enum handler_return long_mode_do_msr_write(struct cpu_user_regs *regs)
         break;
 
     case MSR_IA32_MC4_MISC: /* Threshold register */
+    case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
         /*
          * MCA/MCE: Threshold register is reported to be locked, so we ignore
          * all write accesses. This behaviour matches real HW, so guests should
@@ -1777,6 +1778,7 @@ static void svm_do_msr_access(
             break;
 
         case MSR_IA32_MC4_MISC: /* Threshold register */
+        case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
             /*
              * MCA/MCE: We report that the threshold register is unavailable
              * for OS use (locked by the BIOS).