{
int ret = 0;
+ ASSERT(!is_hardware_domain(d));
+
spin_lock(&d->event_lock);
switch ( type )
{
const struct hvm_irq_dpci *hvm_irq_dpci;
unsigned int machine_gsi = 0;
- if ( *index < 0 || *index >= NR_HVM_IRQS )
+ if ( *index < 0 || *index >= NR_HVM_DOMU_IRQS )
{
ret = -EINVAL;
break;
{
const struct hvm_girq_dpci_mapping *girq;
- BUILD_BUG_ON(ARRAY_SIZE(hvm_irq_dpci->girq) < NR_HVM_IRQS);
+ BUILD_BUG_ON(ARRAY_SIZE(hvm_irq_dpci->girq) < NR_HVM_DOMU_IRQS);
list_for_each_entry ( girq,
&hvm_irq_dpci->girq[*index],
list )
spin_unlock(&d->event_lock);
return -ENOMEM;
}
- for ( i = 0; i < NR_HVM_IRQS; i++ )
+ for ( i = 0; i < NR_HVM_DOMU_IRQS; i++ )
INIT_LIST_HEAD(&hvm_irq_dpci->girq[i]);
hvm_domain_irq(d)->dpci = hvm_irq_dpci;
#define NR_ISAIRQS 16
#define NR_LINK 4
#if defined(CONFIG_X86)
-# define NR_HVM_IRQS VIOAPIC_NUM_PINS
+# define NR_HVM_DOMU_IRQS ARRAY_SIZE(((struct hvm_hw_vioapic *)0)->redirtbl)
#endif
/* Protected by domain's event_lock */
struct hvm_irq_dpci {
/* Guest IRQ to guest device/intx mapping. */
- struct list_head girq[NR_HVM_IRQS];
+ struct list_head girq[NR_HVM_DOMU_IRQS];
/* Record of mapped ISA IRQs */
DECLARE_BITMAP(isairq_map, NR_ISAIRQS);
/* Record of mapped Links */