} else {
ch = ~value;
}
- if (s->chr.chr && s->enable && (s->control[0] & (1 << 3))) { /* TXE */
+ if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
{
PXA2xxFIrState *s = PXA2XX_FIR(dev);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty,
- pxa2xx_fir_rx, pxa2xx_fir_event, s, NULL);
- }
+ qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty,
+ pxa2xx_fir_rx, pxa2xx_fir_event, s, NULL);
}
static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id)
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;
s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size;
- if (s->chr.chr) {
- qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
- }
+ qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
speed, parity, data_bits, stop_bits);
s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s);
s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr,
- strongarm_uart_can_receive,
- strongarm_uart_receive,
- strongarm_uart_event,
- s, NULL);
- }
+ qemu_chr_fe_set_handlers(&s->chr,
+ strongarm_uart_can_receive,
+ strongarm_uart_receive,
+ strongarm_uart_event,
+ s, NULL);
}
static void strongarm_uart_reset(DeviceState *dev)
s->read_pos = 0;
}
}
- if (s->chr.chr) {
- qemu_chr_fe_accept_input(&s->chr);
- }
+ qemu_chr_fe_accept_input(&s->chr);
bcm2835_aux_update(s);
return c;
case AUX_MU_IO_REG:
/* "DLAB bit set means access baudrate register" is NYI */
ch = value;
- if (s->chr.chr) {
- /* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(&s->chr, &ch, 1);
- }
+ /* XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks */
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
break;
case AUX_MU_IER_REG:
{
BCM2835AuxState *s = BCM2835_AUX(dev);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive,
- bcm2835_aux_receive, NULL, s, NULL);
- }
+ qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive,
+ bcm2835_aux_receive, NULL, s, NULL);
}
static Property bcm2835_aux_props[] = {
{
s->rx_wpos = 0;
s->rx_count = 0;
- if (s->chr.chr) {
- qemu_chr_fe_accept_input(&s->chr);
- }
+ qemu_chr_fe_accept_input(&s->chr);
}
static void uart_tx_reset(CadenceUARTState *s)
{
int break_enabled = 1;
- if (s->chr.chr) {
- qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
- &break_enabled);
- }
+ qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
+ &break_enabled);
}
static void uart_parameters_setup(CadenceUARTState *s)
packet_size += ssp.data_bits + ssp.stop_bits;
s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
- if (s->chr.chr) {
- qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
- }
+ qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
static int uart_can_receive(void *opaque)
*c = s->rx_fifo[rx_rpos];
s->rx_count--;
- if (s->chr.chr) {
- qemu_chr_fe_accept_input(&s->chr);
- }
+ qemu_chr_fe_accept_input(&s->chr);
} else {
*c = 0;
}
s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
fifo_trigger_update, s);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
- uart_event, s, NULL);
- }
+ qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
+ uart_event, s, NULL);
}
static void cadence_uart_init(Object *obj)
switch (addr) {
case R_TX:
- if (s->chr.chr) {
- /* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(&s->chr, &ch, 1);
- }
+ /* XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks */
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
break;
case R_ST:
{
DigicUartState *s = DIGIC_UART(dev);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
- uart_event, s, NULL);
- }
+ qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
+ uart_event, s, NULL);
}
static void digic_uart_init(Object *obj)
else
ret = s->rx;
trace_escc_mem_readb_data(CHN_C(s), ret);
- if (s->chr.chr) {
- qemu_chr_fe_accept_input(&s->chr);
- }
+ qemu_chr_fe_accept_input(&s->chr);
return ret;
default:
break;
{
ETRAXSerial *s = ETRAX_SERIAL(dev);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr,
- serial_can_receive, serial_receive,
- serial_event, s, NULL);
- }
+ qemu_chr_fe_set_handlers(&s->chr,
+ serial_can_receive, serial_receive,
+ serial_event, s, NULL);
}
static void etraxfs_ser_class_init(ObjectClass *klass, void *data)
s->usr2 &= ~USR2_RDR;
s->uts1 |= UTS1_RXEMPTY;
imx_update(s);
- if (s->chr.chr) {
- qemu_chr_fe_accept_input(&s->chr);
- }
+ qemu_chr_fe_accept_input(&s->chr);
}
return c;
case 0x10: /* UTXD */
ch = value;
if (s->ucr2 & UCR2_TXEN) {
- if (s->chr.chr) {
- /* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(&s->chr, &ch, 1);
- }
+ /* XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks */
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->usr1 &= ~USR1_TRDY;
imx_update(s);
s->usr1 |= USR1_TRDY;
}
if (value & UCR2_RXEN) {
if (!(s->ucr2 & UCR2_RXEN)) {
- if (s->chr.chr) {
- qemu_chr_fe_accept_input(&s->chr);
- }
+ qemu_chr_fe_accept_input(&s->chr);
}
}
s->ucr2 = value & 0xffff;
{
IMXSerialState *s = IMX_SERIAL(dev);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
- imx_event, s, NULL);
- } else {
- DPRINTF("No char dev for uart\n");
- }
+ DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr));
+
+ qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
+ imx_event, s, NULL);
}
static void imx_serial_init(Object *obj)
if (ch->rx_pending == 0) {
ch->sr &= ~SR_RXRDY;
blk->isr &= ~ISR_RXRDY(channel);
- if (ch->dev.chr) {
- qemu_chr_fe_accept_input(&ch->dev);
- }
+ qemu_chr_fe_accept_input(&ch->dev);
} else {
ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
}
case REG_THRa:
case REG_THRb:
if (ch->sr & SR_TXRDY) {
+ uint8_t thr = reg;
DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
- if (ch->dev.chr) {
- uint8_t thr = reg;
- /* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(&ch->dev, &thr, 1);
- }
+ /* XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks */
+ qemu_chr_fe_write_all(&ch->dev, &thr, 1);
} else {
DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
}
trace_lm32_juart_set_jtx(s->jtx);
s->jtx = jtx;
- if (s->chr.chr) {
- /* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(&s->chr, &ch, 1);
- }
+ /* XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks */
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
}
void lm32_juart_set_jrx(DeviceState *d, uint32_t jtx)
{
LM32JuartState *s = LM32_JUART(dev);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr, juart_can_rx, juart_rx,
- juart_event, s, NULL);
- }
+ qemu_chr_fe_set_handlers(&s->chr, juart_can_rx, juart_rx,
+ juart_event, s, NULL);
}
static const VMStateDescription vmstate_lm32_juart = {
addr >>= 2;
switch (addr) {
case R_RXTX:
- if (s->chr.chr) {
- /* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(&s->chr, &ch, 1);
- }
+ /* XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks */
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
break;
case R_IER:
case R_LCR:
{
LM32UartState *s = LM32_UART(dev);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
- uart_event, s, NULL);
- }
+ qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
+ uart_event, s, NULL);
}
static const VMStateDescription vmstate_lm32_uart = {
static void mcf_uart_do_tx(mcf_uart_state *s)
{
if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
- if (s->chr.chr) {
- /* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(&s->chr, (unsigned char *)&s->tb, 1);
- }
+ /* XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks */
+ qemu_chr_fe_write_all(&s->chr, (unsigned char *)&s->tb, 1);
s->sr |= MCF_UART_TxEMP;
}
if (s->tx_enabled) {
addr >>= 2;
switch (addr) {
case R_RXTX:
- if (s->chr.chr) {
- qemu_chr_fe_write_all(&s->chr, &ch, 1);
- }
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->regs[R_STAT] |= STAT_TX_EVT;
break;
case R_DIV:
{
MilkymistUartState *s = MILKYMIST_UART(dev);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
- uart_event, s, NULL);
- }
+ qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
+ uart_event, s, NULL);
}
static void milkymist_uart_init(Object *obj)
trace_pl011_read_fifo(s->read_count);
s->rsr = c >> 8;
pl011_update(s);
- if (s->chr.chr) {
- qemu_chr_fe_accept_input(&s->chr);
- }
+ qemu_chr_fe_accept_input(&s->chr);
r = c;
break;
case 1: /* UARTRSR */
case 0: /* UARTDR */
/* ??? Check if transmitter is enabled. */
ch = value;
- if (s->chr.chr) {
- /* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(&s->chr, &ch, 1);
- }
+ /* XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks */
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->int_level |= PL011_INT_TX;
pl011_update(s);
break;
{
PL011State *s = PL011(dev);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr, pl011_can_receive, pl011_receive,
- pl011_event, s, NULL);
- }
+ qemu_chr_fe_set_handlers(&s->chr, pl011_can_receive, pl011_receive,
+ pl011_event, s, NULL);
}
static void pl011_class_init(ObjectClass *oc, void *data)
}
console_available = true;
- if (scon->chr.chr) {
- qemu_chr_fe_set_handlers(&scon->chr, chr_can_read,
- chr_read, NULL, scon, NULL);
- }
+ qemu_chr_fe_set_handlers(&scon->chr, chr_can_read,
+ chr_read, NULL, scon, NULL);
return 0;
}
return -1;
}
console_available = true;
- if (scon->chr.chr) {
- qemu_chr_fe_set_handlers(&scon->chr, chr_can_read,
- chr_read, NULL, scon, NULL);
- }
+ qemu_chr_fe_set_handlers(&scon->chr, chr_can_read,
+ chr_read, NULL, scon, NULL);
return 0;
}
case USART_SR:
retvalue = s->usart_sr;
s->usart_sr &= ~USART_SR_TC;
- if (s->chr.chr) {
- qemu_chr_fe_accept_input(&s->chr);
- }
+ qemu_chr_fe_accept_input(&s->chr);
return retvalue;
case USART_DR:
DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
s->usart_sr |= USART_SR_TXE;
s->usart_sr &= ~USART_SR_RXNE;
- if (s->chr.chr) {
- qemu_chr_fe_accept_input(&s->chr);
- }
+ qemu_chr_fe_accept_input(&s->chr);
qemu_set_irq(s->irq, 0);
return s->usart_dr & 0x3FF;
case USART_BRR:
case USART_DR:
if (value < 0xF000) {
ch = value;
- if (s->chr.chr) {
- /* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(&s->chr, &ch, 1);
- }
+ /* XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks */
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->usart_sr |= USART_SR_TC;
s->usart_sr &= ~USART_SR_TXE;
}
{
STM32F2XXUsartState *s = STM32F2XX_USART(dev);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive,
- stm32f2xx_usart_receive, NULL, s, NULL);
- }
+ qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive,
+ stm32f2xx_usart_receive, NULL, s, NULL);
}
static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
DeviceState *dev = DEVICE(port);
VirtIOSerialPortClass *k = VIRTIO_SERIAL_PORT_GET_CLASS(port);
- if (vcon->chr.chr && !k->is_console) {
+ if (!k->is_console) {
qemu_chr_fe_set_open(&vcon->chr, guest_connected);
}
{
VirtConsole *vcon = VIRTIO_CONSOLE(port);
- if (vcon->chr.chr) {
- qemu_chr_fe_accept_input(&vcon->chr);
- }
+ qemu_chr_fe_accept_input(&vcon->chr);
}
/* Readiness of the guest to accept data on a port */
return -1;
xen_be_bind_evtchn(&con->xendev);
- if (con->chr.chr) {
- qemu_chr_fe_set_handlers(&con->chr, xencons_can_receive,
- xencons_receive, NULL, con, NULL);
- }
+ qemu_chr_fe_set_handlers(&con->chr, xencons_can_receive,
+ xencons_receive, NULL, con, NULL);
xen_be_printf(xendev, 1, "ring mfn %d, remote port %d, local port %d, limit %zd\n",
con->ring_ref,
break;
case R_TX:
- if (s->chr.chr) {
- /* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(&s->chr, &ch, 1);
- }
+ /* XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks */
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->regs[addr] = value;
/* hax. */
{
XilinxUARTLite *s = XILINX_UARTLITE(dev);
- if (s->chr.chr) {
- qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
- uart_event, s, NULL);
- }
+ qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
+ uart_event, s, NULL);
}
static void xilinx_uartlite_init(Object *obj)
* @qemu_chr_fe_disconnect:
*
* Close a fd accpeted by character backend.
+ * Without associated CharDriver, do nothing.
*/
void qemu_chr_fe_disconnect(CharBackend *be);
/**
* @qemu_chr_fe_wait_connected:
*
- * Wait for characted backend to be connected.
+ * Wait for characted backend to be connected, return < 0 on error or
+ * if no assicated CharDriver.
*/
int qemu_chr_fe_wait_connected(CharBackend *be, Error **errp);
* Ask the backend to override its normal echo setting. This only really
* applies to the stdio backend and is used by the QMP server such that you
* can see what you type if you try to type QMP commands.
+ * Without associated CharDriver, do nothing.
*
* @echo true to enable echo, false to disable echo
*/
*
* Set character frontend open status. This is an indication that the
* front end is ready (or not) to begin doing I/O.
+ * Without associated CharDriver, do nothing.
*/
void qemu_chr_fe_set_open(CharBackend *be, int fe_open);
/**
* @qemu_chr_fe_event:
*
- * Send an event from the front end to the back end.
+ * Send an event from the front end to the back end. It does nothing
+ * without associated CharDriver.
*
* @event the event to send
*/
/**
* @qemu_chr_fe_printf:
*
- * Write to a character backend using a printf style interface.
- * This function is thread-safe.
+ * Write to a character backend using a printf style interface. This
+ * function is thread-safe. It does nothing without associated
+ * CharDriver.
*
* @fmt see #printf
*/
* If the backend is connected, create and add a #GSource that fires
* when the given condition (typically G_IO_OUT|G_IO_HUP or G_IO_HUP)
* is active; return the #GSource's tag. If it is disconnected,
- * return 0.
+ * or without associated CharDriver, return 0.
*
* @cond the condition to poll for
* @func the function to call when the condition happens
* @buf the data
* @len the number of bytes to send
*
- * Returns: the number of bytes consumed
+ * Returns: the number of bytes consumed (0 if no assicated CharDriver)
*/
int qemu_chr_fe_write(CharBackend *be, const uint8_t *buf, int len);
* @buf the data
* @len the number of bytes to send
*
- * Returns: the number of bytes consumed
+ * Returns: the number of bytes consumed (0 if no assicated CharDriver)
*/
int qemu_chr_fe_write_all(CharBackend *be, const uint8_t *buf, int len);
* @buf the data buffer
* @len the number of bytes to read
*
- * Returns: the number of bytes read
+ * Returns: the number of bytes read (0 if no assicated CharDriver)
*/
int qemu_chr_fe_read_all(CharBackend *be, uint8_t *buf, int len);
* @cmd see CHR_IOCTL_*
* @arg the data associated with @cmd
*
- * Returns: if @cmd is not supported by the backend, -ENOTSUP, otherwise the
- * return value depends on the semantics of @cmd
+ * Returns: if @cmd is not supported by the backend or there is no
+ * associated CharDriver, -ENOTSUP, otherwise the return
+ * value depends on the semantics of @cmd
*/
int qemu_chr_fe_ioctl(CharBackend *be, int cmd, void *arg);
* result in overwriting the fd array with the new value without being send.
* Upon writing the message the fd array is freed.
*
- * Returns: -1 if fd passing isn't supported.
+ * Returns: -1 if fd passing isn't supported or no associated CharDriver.
*/
int qemu_chr_fe_set_msgfds(CharBackend *be, int *fds, int num);
/**
* @qemu_chr_fe_get_driver:
*
- * Returns the driver associated with a CharBackend or NULL.
+ * Returns the driver associated with a CharBackend or NULL if no
+ * associated CharDriver.
*/
CharDriverState *qemu_chr_fe_get_driver(CharBackend *be);
* @qemu_chr_fe_deinit:
*
* Dissociate the CharBackend from the CharDriver.
+ *
+ * Safe to call without associated CharDriver.
*/
void qemu_chr_fe_deinit(CharBackend *b);
*
* Set the front end char handlers. The front end takes the focus if
* any of the handler is non-NULL.
+ *
+ * Without associated CharDriver, nothing is changed.
*/
void qemu_chr_fe_set_handlers(CharBackend *b,
IOCanReadHandler *fd_can_read,
/**
* @qemu_chr_fe_take_focus:
*
- * Take the focus (if the front end is muxed)
+ * Take the focus (if the front end is muxed).
+ *
+ * Without associated CharDriver, nothing is changed.
*/
void qemu_chr_fe_take_focus(CharBackend *b);
CharDriverState *s = be->chr;
int ret;
+ if (!s) {
+ return 0;
+ }
+
if (s->replay && replay_mode == REPLAY_MODE_PLAY) {
int offset;
replay_char_write_event_load(&ret, &offset);
{
CharDriverState *s = be->chr;
+ if (!s) {
+ return 0;
+ }
+
return qemu_chr_write_all(s, buf, len);
}
int offset = 0, counter = 10;
int res;
- if (!s->chr_sync_read) {
+ if (!s || !s->chr_sync_read) {
return 0;
}
-
+
if (s->replay && replay_mode == REPLAY_MODE_PLAY) {
return replay_char_read_all_load(buf);
}
{
CharDriverState *s = be->chr;
int res;
- if (!s->chr_ioctl || s->replay) {
+
+ if (!s || !s->chr_ioctl || s->replay) {
res = -ENOTSUP;
} else {
res = s->chr_ioctl(s, cmd, arg);
CharDriverState *s = be->chr;
int fd;
int res = (qemu_chr_fe_get_msgfds(be, &fd, 1) == 1) ? fd : -1;
- if (s->replay) {
+ if (s && s->replay) {
fprintf(stderr,
"Replay: get msgfd is not supported for serial devices yet\n");
exit(1);
{
CharDriverState *s = be->chr;
+ if (!s) {
+ return -1;
+ }
+
return s->get_msgfds ? s->get_msgfds(s, fds, len) : -1;
}
{
CharDriverState *s = be->chr;
+ if (!s) {
+ return -1;
+ }
+
return s->set_msgfds ? s->set_msgfds(s, fds, num) : -1;
}
{
CharDriverState *s = be->chr;
+ if (!s) {
+ return;
+ }
+
if (s->chr_accept_input)
s->chr_accept_input(s);
qemu_notify_event();
void qemu_chr_fe_take_focus(CharBackend *b)
{
+ if (!b->chr) {
+ return;
+ }
+
if (b->chr->is_mux) {
mux_set_focus(b->chr->opaque, b->tag);
}
int qemu_chr_fe_wait_connected(CharBackend *be, Error **errp)
{
+ if (!be->chr) {
+ error_setg(errp, "missing associated backend");
+ return -1;
+ }
+
return qemu_chr_wait_connected(be->chr, errp);
}
{
CharDriverState *chr = be->chr;
- if (chr->chr_set_echo) {
+ if (chr && chr->chr_set_echo) {
chr->chr_set_echo(chr, echo);
}
}
{
CharDriverState *chr = be->chr;
+ if (!chr) {
+ return;
+ }
+
if (chr->fe_open == fe_open) {
return;
}
{
CharDriverState *chr = be->chr;
- if (chr->chr_fe_event) {
+ if (chr && chr->chr_fe_event) {
chr->chr_fe_event(chr, event);
}
}
GSource *src;
guint tag;
- if (s->chr_add_watch == NULL) {
+ if (!s || s->chr_add_watch == NULL) {
return 0;
}
{
CharDriverState *chr = be->chr;
- if (chr->chr_disconnect) {
+ if (chr && chr->chr_disconnect) {
chr->chr_disconnect(chr);
}
}
projects / qemu-xen.git / commitdiff