Add the BTI instructions and the associated note to make the AArch64 asm
objects compatible with BTI enforcement.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
# );\r
#\r
ASM_PFX(ArmReadIdIsar0):\r
+ AARCH64_BTI(c)\r
mrs x0, id_aa64isar0_el1 // Read ID_AA64ISAR0 Register\r
ret\r
-\r
-\r
# );\r
#\r
ASM_PFX(ArmRndr):\r
+ AARCH64_BTI(c)\r
mrs x1, RNDR\r
str x1, [x0]\r
cset x0, ne // RNDR sets NZCV to 0b0100 on failure\r