]> xenbits.xensource.com Git - people/aperard/xen-unstable.git/commitdiff
xen/arm32: head: Add missing isb in setup_fixmap()
authorJulien Grall <jgrall@amazon.com>
Tue, 4 Jul 2023 18:57:00 +0000 (19:57 +0100)
committerJulien Grall <jgrall@amazon.com>
Tue, 4 Jul 2023 19:07:47 +0000 (20:07 +0100)
Per the Arm Arm (ARM DDI 0406C.d A3.8.3):

"The DMB and DSB memory barriers affect reads and writes to the memory
system generated by load/store instructions and data or unified cache
maintenance operations being executed by the processor. Instruction
fetches or accesses caused by a hardware translation table access are
not explicit accesses."

In setup_fixmap(), we write the fixmap area and may be used soon after,
for instance, to write to the UART. IOW, there could be hardware
translation table access. So we need to ensure the 'dsb' has completed
before continuing. Therefore add an 'isb'.

Fixes: e79999e587d7 ("xen/arm32: head: Remove 1:1 mapping as soon as it is not used")
Signed-off-by: Julien Grall <jgrall@amazon.com>
Reviewed-by: Henry Wang <Henry.Wang@arm.com>
Tested-by: Henry Wang <Henry.Wang@arm.com>
Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
xen/arch/arm/arm32/head.S

index 451579051c1eb8ef9a867adfb377ca2e4c9be068..4cfda2cf70e0a0490817f114dfc4ca302ddeda01 100644 (file)
@@ -791,6 +791,11 @@ setup_fixmap:
         create_table_entry boot_second, xen_fixmap, r0, 2
         /* Ensure any page table updates made above have occurred. */
         dsb   nshst
+        /*
+         * The fixmap area will be used soon after. So ensure no hardware
+         * translation happens before the dsb completes.
+         */
+        isb
 
         mov   pc, lr
 ENDPROC(setup_fixmap)