OvmfPkg/IndustryStandard: Introduce PageTable.h

We are going to use the page table structure in yet another place,
collect the types and macro that can be used from another module
rather than making yet another copy.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>

diff --git a/OvmfPkg/Include/IndustryStandard/PageTable.h b/OvmfPkg/Include/IndustryStandard/PageTable.h
new file mode 100644 (file)
index 0000000..5e797ee
--- /dev/null
+++ b/OvmfPkg/Include/IndustryStandard/PageTable.h
@@ -0,0 +1,161 @@
+/** @file\r
+\r
+  x86_64 Page Tables structures\r
+\r
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.<BR>\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+  Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r
+\r
+**/\r
+\r
+#ifndef PAGE_TABLE_H_\r
+#define PAGE_TABLE_H_\r
+\r
+#include <Base.h>\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// Page-Map Level-4 Offset (PML4) and\r
+// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
+//\r
+\r
+typedef union {\r
+  struct {\r
+    UINT64  Present:1;                // 0 = Not present in memory,\r
+                                      //   1 = Present in memory\r
+    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
+    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
+    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
+                                      //   1 = Write-Through caching\r
+    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
+    UINT64  Accessed:1;               // 0 = Not accessed,\r
+                                      //   1 = Accessed (set by CPU)\r
+    UINT64  Reserved:1;               // Reserved\r
+    UINT64  MustBeZero:2;             // Must Be Zero\r
+    UINT64  Available:3;              // Available for use by system software\r
+    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
+    UINT64  AvabilableHigh:11;        // Available for use by system software\r
+    UINT64  Nx:1;                     // No Execute bit\r
+  } Bits;\r
+  UINT64    Uint64;\r
+} PAGE_MAP_AND_DIRECTORY_POINTER;\r
+\r
+//\r
+// Page Table Entry 4KB\r
+//\r
+typedef union {\r
+  struct {\r
+    UINT64  Present:1;                // 0 = Not present in memory,\r
+                                      //   1 = Present in memory\r
+    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
+    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
+    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
+                                      //   1 = Write-Through caching\r
+    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
+    UINT64  Accessed:1;               // 0 = Not accessed,\r
+                                      //   1 = Accessed (set by CPU)\r
+    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by\r
+                                      //   processor on access to page\r
+    UINT64  PAT:1;                    //\r
+    UINT64  Global:1;                 // 0 = Not global page, 1 = global page\r
+                                      //   TLB not cleared on CR3 write\r
+    UINT64  Available:3;              // Available for use by system software\r
+    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
+    UINT64  AvabilableHigh:11;        // Available for use by system software\r
+    UINT64  Nx:1;                     // 0 = Execute Code,\r
+                                      //   1 = No Code Execution\r
+  } Bits;\r
+  UINT64    Uint64;\r
+} PAGE_TABLE_4K_ENTRY;\r
+\r
+//\r
+// Page Table Entry 2MB\r
+//\r
+typedef union {\r
+  struct {\r
+    UINT64  Present:1;                // 0 = Not present in memory,\r
+                                      //   1 = Present in memory\r
+    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
+    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
+    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
+                                      //   1=Write-Through caching\r
+    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
+    UINT64  Accessed:1;               // 0 = Not accessed,\r
+                                      //   1 = Accessed (set by CPU)\r
+    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by\r
+                                      //   processor on access to page\r
+    UINT64  MustBe1:1;                // Must be 1\r
+    UINT64  Global:1;                 // 0 = Not global page, 1 = global page\r
+                                      //   TLB not cleared on CR3 write\r
+    UINT64  Available:3;              // Available for use by system software\r
+    UINT64  PAT:1;                    //\r
+    UINT64  MustBeZero:8;             // Must be zero;\r
+    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
+    UINT64  AvabilableHigh:11;        // Available for use by system software\r
+    UINT64  Nx:1;                     // 0 = Execute Code,\r
+                                      //   1 = No Code Execution\r
+  } Bits;\r
+  UINT64    Uint64;\r
+} PAGE_TABLE_ENTRY;\r
+\r
+//\r
+// Page Table Entry 1GB\r
+//\r
+typedef union {\r
+  struct {\r
+    UINT64  Present:1;                // 0 = Not present in memory,\r
+                                      //   1 = Present in memory\r
+    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
+    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
+    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
+                                      //   1 = Write-Through caching\r
+    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
+    UINT64  Accessed:1;               // 0 = Not accessed,\r
+                                      //   1 = Accessed (set by CPU)\r
+    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by\r
+                                      //   processor on access to page\r
+    UINT64  MustBe1:1;                // Must be 1\r
+    UINT64  Global:1;                 // 0 = Not global page, 1 = global page\r
+                                      //   TLB not cleared on CR3 write\r
+    UINT64  Available:3;              // Available for use by system software\r
+    UINT64  PAT:1;                    //\r
+    UINT64  MustBeZero:17;            // Must be zero;\r
+    UINT64  PageTableBaseAddress:22;  // Page Table Base Address\r
+    UINT64  AvabilableHigh:11;        // Available for use by system software\r
+    UINT64  Nx:1;                     // 0 = Execute Code,\r
+                                      //   1 = No Code Execution\r
+  } Bits;\r
+  UINT64    Uint64;\r
+} PAGE_TABLE_1G_ENTRY;\r
+\r
+#pragma pack()\r
+\r
+#define IA32_PG_P                   BIT0\r
+#define IA32_PG_RW                  BIT1\r
+#define IA32_PG_PS                  BIT7\r
+\r
+#define PAGING_PAE_INDEX_MASK       0x1FF\r
+\r
+#define PAGING_4K_ADDRESS_MASK_64   0x000FFFFFFFFFF000ull\r
+#define PAGING_2M_ADDRESS_MASK_64   0x000FFFFFFFE00000ull\r
+#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
+\r
+#define PAGING_L1_ADDRESS_SHIFT     12\r
+#define PAGING_L2_ADDRESS_SHIFT     21\r
+#define PAGING_L3_ADDRESS_SHIFT     30\r
+#define PAGING_L4_ADDRESS_SHIFT     39\r
+\r
+#define PAGING_PML4E_NUMBER         4\r
+\r
+#define PAGETABLE_ENTRY_MASK        ((1UL << 9) - 1)\r
+#define PML4_OFFSET(x)              ( (x >> 39) & PAGETABLE_ENTRY_MASK)\r
+#define PDP_OFFSET(x)               ( (x >> 30) & PAGETABLE_ENTRY_MASK)\r
+#define PDE_OFFSET(x)               ( (x >> 21) & PAGETABLE_ENTRY_MASK)\r
+#define PTE_OFFSET(x)               ( (x >> 12) & PAGETABLE_ENTRY_MASK)\r
+#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
+\r
+#endif\r

diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
index 996f94f07ebbd21e5e29e5e12c60ff2b570d043d..fe2a0b2826cdd6c1703927b770be8c2d6cc5883f 100644 (file)
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
@@ -14,6 +14,7 @@
 #ifndef __VIRTUAL_MEMORY__\r
 #define __VIRTUAL_MEMORY__\r
 \r
+#include <IndustryStandard/PageTable.h>\r
 #include <Library/BaseLib.h>\r
 #include <Library/BaseMemoryLib.h>\r
 #include <Library/CacheMaintenanceLib.h>\r
@@ -23,148 +24,6 @@
 \r
 #define SYS_CODE64_SEL 0x38\r
 \r
-#pragma pack(1)\r
-\r
-//\r
-// Page-Map Level-4 Offset (PML4) and\r
-// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
-//\r
-\r
-typedef union {\r
-  struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory,\r
-                                      //   1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
-                                      //   1 = Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed,\r
-                                      //   1 = Accessed (set by CPU)\r
-    UINT64  Reserved:1;               // Reserved\r
-    UINT64  MustBeZero:2;             // Must Be Zero\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // No Execute bit\r
-  } Bits;\r
-  UINT64    Uint64;\r
-} PAGE_MAP_AND_DIRECTORY_POINTER;\r
-\r
-//\r
-// Page Table Entry 4KB\r
-//\r
-typedef union {\r
-  struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory,\r
-                                      //   1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
-                                      //   1 = Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed,\r
-                                      //   1 = Accessed (set by CPU)\r
-    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by\r
-                                      //   processor on access to page\r
-    UINT64  PAT:1;                    //\r
-    UINT64  Global:1;                 // 0 = Not global page, 1 = global page\r
-                                      //   TLB not cleared on CR3 write\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // 0 = Execute Code,\r
-                                      //   1 = No Code Execution\r
-  } Bits;\r
-  UINT64    Uint64;\r
-} PAGE_TABLE_4K_ENTRY;\r
-\r
-//\r
-// Page Table Entry 2MB\r
-//\r
-typedef union {\r
-  struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory,\r
-                                      //   1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
-                                      //   1=Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed,\r
-                                      //   1 = Accessed (set by CPU)\r
-    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by\r
-                                      //   processor on access to page\r
-    UINT64  MustBe1:1;                // Must be 1\r
-    UINT64  Global:1;                 // 0 = Not global page, 1 = global page\r
-                                      //   TLB not cleared on CR3 write\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PAT:1;                    //\r
-    UINT64  MustBeZero:8;             // Must be zero;\r
-    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // 0 = Execute Code,\r
-                                      //   1 = No Code Execution\r
-  } Bits;\r
-  UINT64    Uint64;\r
-} PAGE_TABLE_ENTRY;\r
-\r
-//\r
-// Page Table Entry 1GB\r
-//\r
-typedef union {\r
-  struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory,\r
-                                      //   1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
-                                      //   1 = Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed,\r
-                                      //   1 = Accessed (set by CPU)\r
-    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by\r
-                                      //   processor on access to page\r
-    UINT64  MustBe1:1;                // Must be 1\r
-    UINT64  Global:1;                 // 0 = Not global page, 1 = global page\r
-                                      //   TLB not cleared on CR3 write\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PAT:1;                    //\r
-    UINT64  MustBeZero:17;            // Must be zero;\r
-    UINT64  PageTableBaseAddress:22;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // 0 = Execute Code,\r
-                                      //   1 = No Code Execution\r
-  } Bits;\r
-  UINT64    Uint64;\r
-} PAGE_TABLE_1G_ENTRY;\r
-\r
-#pragma pack()\r
-\r
-#define IA32_PG_P                   BIT0\r
-#define IA32_PG_RW                  BIT1\r
-#define IA32_PG_PS                  BIT7\r
-\r
-#define PAGING_PAE_INDEX_MASK       0x1FF\r
-\r
-#define PAGING_4K_ADDRESS_MASK_64   0x000FFFFFFFFFF000ull\r
-#define PAGING_2M_ADDRESS_MASK_64   0x000FFFFFFFE00000ull\r
-#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
-\r
-#define PAGING_L1_ADDRESS_SHIFT     12\r
-#define PAGING_L2_ADDRESS_SHIFT     21\r
-#define PAGING_L3_ADDRESS_SHIFT     30\r
-#define PAGING_L4_ADDRESS_SHIFT     39\r
-\r
-#define PAGING_PML4E_NUMBER         4\r
-\r
-#define PAGETABLE_ENTRY_MASK        ((1UL << 9) - 1)\r
-#define PML4_OFFSET(x)              ( (x >> 39) & PAGETABLE_ENTRY_MASK)\r
-#define PDP_OFFSET(x)               ( (x >> 30) & PAGETABLE_ENTRY_MASK)\r
-#define PDE_OFFSET(x)               ( (x >> 21) & PAGETABLE_ENTRY_MASK)\r
-#define PTE_OFFSET(x)               ( (x >> 12) & PAGETABLE_ENTRY_MASK)\r
-#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
-\r
 #define PAGE_TABLE_POOL_ALIGNMENT   BASE_2MB\r
 #define PAGE_TABLE_POOL_UNIT_SIZE   SIZE_2MB\r
 #define PAGE_TABLE_POOL_UNIT_PAGES  \\r