IntelFsp2Pkg: Fix NASM X64 build warnings.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4377

Fix below warnings generated by NASM X64 build:
/X64/FspHelper.iii:26: warning: signed dword value exceeds bounds
/X64/FspHelper.iii:35: warning: signed dword value exceeds bounds
/X64/FspApiEntryT.iii:320: warning: dword data exceeds bounds

Also replaced "cmp reg, 0" with "test reg, reg" per optimization
suggestion.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index cdebe90fab31c8d0335141a242ff5d476818d8e4..b32fa32a89282fbc29d27408dbf95443191da095 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -135,9 +135,9 @@ ASM_PFX(LoadMicrocodeDefault):
    ;\r
    LOAD_RBP\r
 \r
-   cmp    rsp, 0\r
+   test   rsp, rsp\r
    jz     ParamError\r
-   cmp    rcx, 0\r
+   test   rcx, rcx\r
    jz     ParamError\r
    mov    rsp, rcx\r
 \r
@@ -151,13 +151,13 @@ ASM_PFX(LoadMicrocodeDefault):
 \r
    ; UPD structure is compliant with FSP spec 2.4\r
    mov    rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
-   cmp    rax, 0\r
+   test   rax, rax\r
    jz     Exit2\r
    cmp    rax, 0800h\r
    jl     ParamError\r
 \r
    mov    rsi, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
-   cmp    rsi, 0\r
+   test   rsi, rsi\r
    jnz    CheckMainHeader\r
 \r
 ParamError:\r
@@ -315,9 +315,9 @@ Done:
    mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
    rdmsr                         ; Get current microcode signature\r
    xor   eax, eax\r
-   cmp   edx, 0\r
+   test  edx, edx\r
    jnz   Exit2\r
-   mov   eax, 0800000000000000Eh\r
+   mov   rax, 0800000000000000Eh\r
 \r
 Exit2:\r
    jmp   rbp\r
@@ -464,7 +464,7 @@ ParamValid:
   ; Sec Platform Init\r
   ;\r
   CALL_YMM  ASM_PFX(SecPlatformInit)\r
-  cmp       eax, 0\r
+  test      rax, rax\r
   jnz       TempRamInitExit\r
 \r
   ; Load microcode\r
@@ -476,12 +476,12 @@ ParamValid:
   ; Call Sec CAR Init\r
   LOAD_RCX\r
   CALL_YMM  ASM_PFX(SecCarInit)\r
-  cmp       rax, 0\r
+  test      rax, rax\r
   jnz       TempRamInitExit\r
 \r
   LOAD_RCX\r
   CALL_YMM  ASM_PFX(EstablishStackFsp)\r
-  cmp       rax, 0\r
+  test      rax, rax\r
   jnz       TempRamInitExit\r
 \r
   LOAD_UCODE_STATUS rax             ; Restore microcode status if no CAR init error from SLOT 0 in YMM9 (upper 128bits).\r

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
index 71624a3aad734bc86e61cefc66a4e704cbf74dee..32a60270b81db636c3a5165ff624a3e70cf9746c 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
@@ -23,7 +23,6 @@ ASM_PFX(AsmGetFspInfoHeader):
 global ASM_PFX(FspInfoHeaderRelativeOff)\r
 ASM_PFX(FspInfoHeaderRelativeOff):\r
    DD    0x12345678               ; This value must be patched by the build script\r
-   and   rax, 0xffffffff\r
    ret\r
 \r
 global ASM_PFX(AsmGetFspInfoHeaderNoStack)\r
@@ -32,5 +31,4 @@ ASM_PFX(AsmGetFspInfoHeaderNoStack):
    lea   rcx, [ASM_PFX(FspInfoHeaderRelativeOff)]\r
    mov   ecx, [rcx]\r
    sub   rax, rcx\r
-   and   rax, 0xffffffff\r
    jmp   rdi\r