]> xenbits.xensource.com Git - people/liuw/libxenctrl-split/qemu-xen.git/commitdiff
target-ppc: Introduce DFP Test Significance
authorTom Musta <tommusta@gmail.com>
Mon, 21 Apr 2014 20:55:09 +0000 (15:55 -0500)
committerAlexander Graf <agraf@suse.de>
Mon, 16 Jun 2014 11:24:31 +0000 (13:24 +0200)
Add emulation of the PowerPC Decimal Floating Point Test Significance
instructions dtstsf[q][.].

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc/dfp_helper.c
target-ppc/helper.h
target-ppc/translate.c

index 43eb70d9648e7e0c9fd7a00a47e632d7255ea063..574956a19f022a5ed37513bd37598505043c561c 100644 (file)
@@ -536,3 +536,38 @@ uint32_t helper_##op(CPUPPCState *env, uint64_t *a, uint64_t *b)         \
 
 DFP_HELPER_TSTEX(dtstex, 64)
 DFP_HELPER_TSTEX(dtstexq, 128)
+
+#define DFP_HELPER_TSTSF(op, size)                                       \
+uint32_t helper_##op(CPUPPCState *env, uint64_t *a, uint64_t *b)         \
+{                                                                        \
+    struct PPC_DFP dfp;                                                  \
+    unsigned k;                                                          \
+                                                                         \
+    dfp_prepare_decimal##size(&dfp, 0, b, env);                          \
+                                                                         \
+    k = *a & 0x3F;                                                       \
+                                                                         \
+    if (unlikely(decNumberIsSpecial(&dfp.b))) {                          \
+        dfp.crbf = 1;                                                    \
+    } else if (k == 0) {                                                 \
+        dfp.crbf = 4;                                                    \
+    } else if (unlikely(decNumberIsZero(&dfp.b))) {                      \
+        /* Zero has no sig digits */                                     \
+        dfp.crbf = 4;                                                    \
+    } else {                                                             \
+        unsigned nsd = dfp.b.digits;                                     \
+        if (k < nsd) {                                                   \
+            dfp.crbf = 8;                                                \
+        } else if (k > nsd) {                                            \
+            dfp.crbf = 4;                                                \
+        } else {                                                         \
+            dfp.crbf = 2;                                                \
+        }                                                                \
+    }                                                                    \
+                                                                         \
+    dfp_set_FPCC_from_CRBF(&dfp);                                        \
+    return dfp.crbf;                                                     \
+}
+
+DFP_HELPER_TSTSF(dtstsf, 64)
+DFP_HELPER_TSTSF(dtstsfq, 128)
index 8ffb80651b4abe5caec8a299f968200e517dfdbb..2b39d2a70517ca0586893645c5c5ac759d03b1b2 100644 (file)
@@ -634,3 +634,5 @@ DEF_HELPER_3(dtstdg, i32, env, fprp, i32)
 DEF_HELPER_3(dtstdgq, i32, env, fprp, i32)
 DEF_HELPER_3(dtstex, i32, env, fprp, fprp)
 DEF_HELPER_3(dtstexq, i32, env, fprp, fprp)
+DEF_HELPER_3(dtstsf, i32, env, fprp, fprp)
+DEF_HELPER_3(dtstsfq, i32, env, fprp, fprp)
index 373e8ea5876aafa6bc4486bcb4e784875ed2e586..c99019108657acb516bbcb8a10cac52666f27f03 100644 (file)
@@ -8374,6 +8374,8 @@ GEN_DFP_BF_A_DCM(dtstdg)
 GEN_DFP_BF_A_DCM(dtstdgq)
 GEN_DFP_BF_A_B(dtstex)
 GEN_DFP_BF_A_B(dtstexq)
+GEN_DFP_BF_A_B(dtstsf)
+GEN_DFP_BF_A_B(dtstsfq)
 /***                           SPE extension                               ***/
 /* Register moves */
 
@@ -11319,6 +11321,8 @@ GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
+GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
+GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
 #undef GEN_SPE
 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
     GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)