Fix slti/sltiu for MIPS64, by Aurelien Jarno.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2833 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-mips/op.c b/target-mips/op.c
index 5e3c7973235fd132934f2d31f3a295dc4d0a6e70..c60871afeab948517a64b10ea10b67cf4dfb1d09 100644 (file)
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -928,14 +928,14 @@ void glue(op_, name) (void) \
 
 OP_COND(eq, T0 == T1);
 OP_COND(ne, T0 != T1);
-OP_COND(ge, (int32_t)T0 >= (int32_t)T1);
+OP_COND(ge, (target_long)T0 >= (target_long)T1);
 OP_COND(geu, T0 >= T1);
-OP_COND(lt, (int32_t)T0 < (int32_t)T1);
+OP_COND(lt, (target_long)T0 < (target_long)T1);
 OP_COND(ltu, T0 < T1);
-OP_COND(gez, (int32_t)T0 >= 0);
-OP_COND(gtz, (int32_t)T0 > 0);
-OP_COND(lez, (int32_t)T0 <= 0);
-OP_COND(ltz, (int32_t)T0 < 0);
+OP_COND(gez, (target_long)T0 >= 0);
+OP_COND(gtz, (target_long)T0 > 0);
+OP_COND(lez, (target_long)T0 <= 0);
+OP_COND(ltz, (target_long)T0 < 0);
 
 /* Branches */
 void OPPROTO op_goto_tb0(void)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index a360d11fc1a14ee2bd701faeba933308f6eda49a..0396ac396dddc9ef8ec4307c31290903d59047fa 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -921,7 +921,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
 static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
                            int rs, int16_t imm)
 {
-    uint32_t uimm;
+    target_ulong uimm;
     const char *opn = "imm arith";
 
     if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
@@ -941,7 +941,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
 #endif
     case OPC_SLTI:
     case OPC_SLTIU:
-        uimm = (int32_t)imm; /* Sign extend to 32 bits */
+        uimm = (target_long)imm; /* Sign extend to 32/64 bits */
         /* Fall through. */
     case OPC_ANDI:
     case OPC_ORI: