UefiCpuPkg/CpuDxe: Refactor to use CPUID definitions

The patch does not change any code behavior but only refactors by:
* replaces the hardcode 0x80000000 with CPUID_EXTENDED_FUNCTION
* replaces the hardcode 0x80000008 with CPUID_VIR_PHY_ADDRESS_SIZE
* replace "UINT32 Eax" with
   "CPUID_VIR_PHY_ADDRESS_SIZE_EAX  VirPhyAddressSize"

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ahmad Anadani <ahmad.anadani@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c
index a6a91507f6066fbce11911530b083abe9904a658..920976c5766b4b2964238fb3edb53b1da6cc2eff 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.c
@@ -1,7 +1,7 @@
 /** @file\r
   CPU DXE Module to produce CPU ARCH Protocol.\r
 \r
-  Copyright (c) 2008 - 2022, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -505,20 +505,18 @@ InitializeMtrrMask (
   VOID\r
   )\r
 {\r
-  UINT32  RegEax;\r
-  UINT8   PhysicalAddressBits;\r
+  UINT32                          MaxExtendedFunction;\r
+  CPUID_VIR_PHY_ADDRESS_SIZE_EAX  VirPhyAddressSize;\r
 \r
-  AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
+  AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);\r
 \r
-  if (RegEax >= 0x80000008) {\r
-    AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
-\r
-    PhysicalAddressBits = (UINT8)RegEax;\r
+  if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {\r
+    AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);\r
   } else {\r
-    PhysicalAddressBits = 36;\r
+    VirPhyAddressSize.Bits.PhysicalAddressBits = 36;\r
   }\r
 \r
-  mValidMtrrBitsMask    = LShiftU64 (1, PhysicalAddressBits) - 1;\r
+  mValidMtrrBitsMask    = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;\r
   mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;\r
 }\r
 \r

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.h b/UefiCpuPkg/CpuDxe/CpuDxe.h
index 49a390b4c404f5ecd921467a9cfd564fc079798a..0e7d88dd357c42d2d6c522c2afe7303467f4452b 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuDxe.h
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.h
@@ -1,7 +1,7 @@
 /** @file\r
   CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol.\r
 \r
-  Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -13,6 +13,7 @@
 \r
 #include <Protocol/Cpu.h>\r
 #include <Protocol/MpService.h>\r
+#include <Register/Intel/Cpuid.h>\r
 #include <Register/Intel/Msr.h>\r
 \r
 #include <Ppi/SecPlatformInformation.h>\r