]> xenbits.xensource.com Git - people/pauldu/qemu.git/commitdiff
target/arm: make pmccntr_op_start/finish static
authorAndrew Jones <drjones@redhat.com>
Mon, 25 Mar 2019 14:16:47 +0000 (14:16 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Mon, 25 Mar 2019 14:16:47 +0000 (14:16 +0000)
These functions are not used outside helper.c

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190322162333.17159-4-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/cpu.h
target/arm/helper.c

index 5f23c621325c12cde198c171881a5c86646561ef..d4d2836923df5b25e97fd0c479354290ffb0f8e5 100644 (file)
@@ -992,17 +992,6 @@ static inline bool is_a64(CPUARMState *env)
 int cpu_arm_signal_handler(int host_signum, void *pinfo,
                            void *puc);
 
-/**
- * pmccntr_op_start/finish
- * @env: CPUARMState
- *
- * Convert the counter in the PMCCNTR between its delta form (the typical mode
- * when it's enabled) and the guest-visible value. These two calls must always
- * surround any action which might affect the counter.
- */
-void pmccntr_op_start(CPUARMState *env);
-void pmccntr_op_finish(CPUARMState *env);
-
 /**
  * pmu_op_start/finish
  * @env: CPUARMState
index fc73488f6cc0606859ce2558e36e5d9360f744b7..a36f4b3d69976bbf117c9e49b8578c0ebdc33a70 100644 (file)
@@ -1337,7 +1337,7 @@ static void pmu_update_irq(CPUARMState *env)
  * etc. can be done logically. This is essentially a no-op if the counter is
  * not enabled at the time of the call.
  */
-void pmccntr_op_start(CPUARMState *env)
+static void pmccntr_op_start(CPUARMState *env)
 {
     uint64_t cycles = cycles_get_count(env);
 
@@ -1367,7 +1367,7 @@ void pmccntr_op_start(CPUARMState *env)
  * guest-visible count. A call to pmccntr_op_finish should follow every call to
  * pmccntr_op_start.
  */
-void pmccntr_op_finish(CPUARMState *env)
+static void pmccntr_op_finish(CPUARMState *env)
 {
     if (pmu_counter_enabled(env, 31)) {
 #ifndef CONFIG_USER_ONLY