For consistency, align the address to the cache line before using it,

  when invalidating the instruction cache.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3449 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-ppc/op_helper_mem.h b/target-ppc/op_helper_mem.h
index a395e02626d7329f69507d3774a22c651dbb36d7..e8aa6407c2831c80b4c8198215c860bd31d7a436 100644 (file)
--- a/target-ppc/op_helper_mem.h
+++ b/target-ppc/op_helper_mem.h
@@ -252,8 +252,8 @@ void glue(do_icbi, MEMSUFFIX) (void)
      * (not a fetch) by the MMU. To be sure it will be so,
      * do the load "by hand".
      */
-    tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0);
     T0 &= ~(env->icache_line_size - 1);
+    tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0);
     tb_invalidate_page_range((uint32_t)T0,
                              (uint32_t)(T0 + env->icache_line_size));
 }
@@ -267,8 +267,8 @@ void glue(do_icbi_64, MEMSUFFIX) (void)
      * (not a fetch) by the MMU. To be sure it will be so,
      * do the load "by hand".
      */
-    tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0);
     T0 &= ~(env->icache_line_size - 1);
+    tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0);
     tb_invalidate_page_range((uint64_t)T0,
                              (uint64_t)(T0 + env->icache_line_size));
 }