x86: add UMIP feature bit

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

diff --git a/include/arch/x86/processor.h b/include/arch/x86/processor.h
index 01069544779e483ca7d0ed275a3fe520a839015c..e2a2cbbef2bf2430345f16a5b37518b66cda2f42 100644 (file)
--- a/include/arch/x86/processor.h
+++ b/include/arch/x86/processor.h
@@ -52,6 +52,7 @@
 #define X86_CR4_PCE             0x00000100  /* Performance counters at ipl 3  */
 #define X86_CR4_OSFXSR          0x00000200  /* Fast FPU save and restore      */
 #define X86_CR4_OSXMMEXCPT      0x00000400  /* Unmasked SSE exceptions        */
+#define X86_CR4_UMIP            0x00000800  /* UMIP                           */
 #define X86_CR4_VMXE            0x00002000  /* VMX                            */
 #define X86_CR4_SMXE            0x00004000  /* SMX                            */
 #define X86_CR4_FSGSBASE        0x00010000  /* {rd,wr}{fs,gs}base             */

diff --git a/include/xen/arch-x86/cpufeatureset.h b/include/xen/arch-x86/cpufeatureset.h
index 905e8e8599a6a96c3c31740bc81488008613e2f5..f66a4ab11dd5a04b9fb9b2af06345ed7d6a6dfa5 100644 (file)
--- a/include/xen/arch-x86/cpufeatureset.h
+++ b/include/xen/arch-x86/cpufeatureset.h
@@ -144,6 +144,7 @@
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */
 #define X86_FEATURE_PREFETCHWT1   (6*32+ 0) /* PREFETCHWT1 instruction */
+#define X86_FEATURE_UMIP          (6*32+ 2) /* User-Mode Instruction Prevention */
 #define X86_FEATURE_PKU           (6*32+ 3) /* Protection Keys for Userspace */
 #define X86_FEATURE_OSPKE         (6*32+ 4) /* OS Protection Keys Enable */