amend "x86/spec-ctrl: CPUID/MSR definitions for L1D_FLUSH"

This is part of XSA-273 / CVE-2018-3646.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>

diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h
index eb24c535619500c9f13695323989eb91a10c421b..ccbf2e35814eba6ad2c430da02953fbd4f90d80e 100644 (file)
--- a/tools/libxc/xc_cpufeature.h
+++ b/tools/libxc/xc_cpufeature.h
@@ -147,6 +147,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (edx) */
 #define X86_FEATURE_IBRSB       26 /* IBRS and IBPB support (used by Intel) */
 #define X86_FEATURE_STIBP       27 /* STIBP */
+#define X86_FEATURE_L1D_FLUSH   28 /* MSR_FLUSH_CMD and L1D flush. */
 #define X86_FEATURE_SSBD        31 /* MSR_SPEC_CTRL.SSBD available */
 
 #endif /* __LIBXC_CPUFEATURE_H */

diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 26cd47506521b25a982fcbce3d5e1d9f3eb8ba22..f5f0eb53572d2c0f966eef8ddd4f1cd150fa31c5 100644 (file)
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -370,6 +370,7 @@ static void xc_cpuid_hvm_policy(
                         bitmaskof(X86_FEATURE_FSGSBASE));
             regs[3] &= (bitmaskof(X86_FEATURE_IBRSB) |
                         bitmaskof(X86_FEATURE_STIBP) |
+                        bitmaskof(X86_FEATURE_L1D_FLUSH) |
                         bitmaskof(X86_FEATURE_SSBD));
         } else
             regs[1] = regs[3] = 0;

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 702dd1a87240b7a70b4bd0dbb5a12438e186167e..1ce03b12b3c266ac653afd12f30733d8b1efa879 100644 (file)
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -4627,6 +4627,8 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx,
             if ( !boot_cpu_has(X86_FEATURE_SC_MSR_HVM) )
                 *edx &= ~(cpufeat_mask(X86_FEATURE_IBRSB) |
                           cpufeat_mask(X86_FEATURE_SSBD));
+            if ( !boot_cpu_has(X86_FEATURE_L1D_FLUSH) )
+                *edx &= ~cpufeat_mask(X86_FEATURE_L1D_FLUSH);
 
             /*
              * Override STIBP to match IBRS.  Guests can safely use STIBP

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 58450558241cb0d8f6d3e5cd64cc79a50825dfdf..a36ae95d140a44fd3a5028eed64f8c41746a49e9 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -882,6 +882,7 @@ void pv_cpuid(struct cpu_user_regs *regs)
                 if ( !boot_cpu_has(X86_FEATURE_SC_MSR_PV) )
                     d &= ~(cpufeat_mask(X86_FEATURE_IBRSB) |
                            cpufeat_mask(X86_FEATURE_SSBD));
+                d &= ~cpufeat_mask(X86_FEATURE_L1D_FLUSH);
 
                 /*
                  * Override STIBP to match IBRS.  Guests can safely use STIBP