x86: drop old (32-bit-only) MSR definitions

Some of them aren't liked by Misra rule 7.2; rather than fixing them,
drop the affected ones and a few more that aren't used (anymore). (Note
that e.g. some MSR_K7_* are applicable on K8 and newer as well, so need
retaining.)

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>

diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 4f861c0bb4785107567f7888bc5dfdac6b64ed3c..2382fc8e1181dae4fe22610c9de12dab5eecd4f1 100644 (file)
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -334,7 +334,6 @@
 #define MSR_K7_EVNTSEL3                        0xc0010003
 #define MSR_K7_PERFCTR3                        0xc0010007
 #define MSR_K8_TOP_MEM1                        0xc001001a
-#define MSR_K7_CLK_CTL                 0xc001001b
 #define MSR_K8_TOP_MEM2                        0xc001001d
 
 #define MSR_K8_HWCR                    0xc0010015
@@ -427,46 +426,11 @@
 #define MSR_AMD_PPIN_CTL                0xc00102f0
 #define MSR_AMD_PPIN                    0xc00102f1
 
-/* K6 MSRs */
-#define MSR_K6_EFER                    0xc0000080
-#define MSR_K6_STAR                    0xc0000081
-#define MSR_K6_WHCR                    0xc0000082
-#define MSR_K6_UWCCR                   0xc0000085
-#define MSR_K6_EPMR                    0xc0000086
-#define MSR_K6_PSOR                    0xc0000087
-#define MSR_K6_PFIR                    0xc0000088
-
-/* Centaur-Hauls/IDT defined MSRs. */
-#define MSR_IDT_FCR1                   0x00000107
-#define MSR_IDT_FCR2                   0x00000108
-#define MSR_IDT_FCR3                   0x00000109
-#define MSR_IDT_FCR4                   0x0000010a
-
-#define MSR_IDT_MCR0                   0x00000110
-#define MSR_IDT_MCR1                   0x00000111
-#define MSR_IDT_MCR2                   0x00000112
-#define MSR_IDT_MCR3                   0x00000113
-#define MSR_IDT_MCR4                   0x00000114
-#define MSR_IDT_MCR5                   0x00000115
-#define MSR_IDT_MCR6                   0x00000116
-#define MSR_IDT_MCR7                   0x00000117
-#define MSR_IDT_MCR_CTRL               0x00000120
-
 /* VIA Cyrix defined MSRs*/
 #define MSR_VIA_FCR                    0x00001107
-#define MSR_VIA_LONGHAUL               0x0000110a
 #define MSR_VIA_RNG                    0x0000110b
-#define MSR_VIA_BCR2                   0x00001147
-
-/* Transmeta defined MSRs */
-#define MSR_TMTA_LONGRUN_CTRL          0x80868010
-#define MSR_TMTA_LONGRUN_FLAGS         0x80868011
-#define MSR_TMTA_LRTI_READOUT          0x80868018
-#define MSR_TMTA_LRTI_VOLT_MHZ         0x8086801a
 
 /* Intel defined MSRs. */
-#define MSR_IA32_P5_MC_ADDR            0x00000000
-#define MSR_IA32_P5_MC_TYPE            0x00000001
 #define MSR_IA32_TSC                   0x00000010
 #define MSR_IA32_PLATFORM_ID           0x00000017
 #define MSR_IA32_EBL_CR_POWERON                0x0000002a