container_of(bridge->ops, const struct pci_ecam_ops, pci_ops);
unsigned int devfn_shift = ops->bus_shift - 8;
void __iomem *base;
-
- unsigned int busn = PCI_BUS(sbdf.bdf);
+ unsigned int busn = sbdf.bus;
if ( busn < cfg->busn_start || busn > cfg->busn_end )
return NULL;
busn -= cfg->busn_start;
base = cfg->win + (busn << ops->bus_shift);
- return base + (PCI_DEVFN2(sbdf.bdf) << devfn_shift) + where;
+ return base + (sbdf.devfn << devfn_shift) + where;
}
bool __init pci_ecam_need_p2m_hwdom_mapping(struct domain *d,
pbus = dev->info.physfn.bus;
pslot = PCI_SLOT(dev->info.physfn.devfn);
pfunc = PCI_FUNC(dev->info.physfn.devfn);
- vf = PCI_BDF2(dev->bus, dev->devfn);
+ vf = dev->sbdf.bdf;
}
table_paddr = read_pci_mem_bar(seg, pbus, pslot, pfunc, bir, vf);
qinval_entry->q.dev_iotlb_inv_dsc.lo.res_1 = 0;
qinval_entry->q.dev_iotlb_inv_dsc.lo.max_invs_pend = pdev->ats.queue_depth;
qinval_entry->q.dev_iotlb_inv_dsc.lo.res_2 = 0;
- qinval_entry->q.dev_iotlb_inv_dsc.lo.sid = PCI_BDF2(pdev->bus, pdev->devfn);
+ qinval_entry->q.dev_iotlb_inv_dsc.lo.sid = pdev->sbdf.bdf;
qinval_entry->q.dev_iotlb_inv_dsc.lo.res_3 = 0;
qinval_entry->q.dev_iotlb_inv_dsc.hi.size = size;