x86/Intel: unlock CPUID earlier for the BSP

Intel CPUs have a MSR bit to limit CPUID enumeration to leaf two. If
this bit is set by the BIOS then CPUID evaluation does not work when
data from any leaf greater than two is needed; early_cpu_init() in
particular wants to collect leaf 7 data.

Cure this by unlocking CPUID right before evaluating anything which
depends on the maximum CPUID leaf being greater than two.

Inspired by (and description cloned from) Linux commit 0c2f6d04619e
("x86/topology/intel: Unlock CPUID before evaluating anything").

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
master commit: fa4d026737a47cd1d66ffb797a29150b4453aa9f
master date: 2024-06-18 15:12:44 +0200

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 88855f5773ee9bdf996fbfcd7941451b38700c37..14a3a97806f01135329494915ee298b7f498854b 100644 (file)
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -343,7 +343,8 @@ void __init early_cpu_init(void)
 
        c->x86_vendor = x86_cpuid_lookup_vendor(ebx, ecx, edx);
        switch (c->x86_vendor) {
-       case X86_VENDOR_INTEL:    actual_cpu = intel_cpu_dev;    break;
+       case X86_VENDOR_INTEL:    intel_unlock_cpuid_leaves(c);
+                                 actual_cpu = intel_cpu_dev;    break;
        case X86_VENDOR_AMD:      actual_cpu = amd_cpu_dev;      break;
        case X86_VENDOR_CENTAUR:  actual_cpu = centaur_cpu_dev;  break;
        case X86_VENDOR_SHANGHAI: actual_cpu = shanghai_cpu_dev; break;

diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h
index 85a67771f7b7d8b267e14dc62de1d6007efc1744..bbde5e528a2658391a8a04a96ff5ed592d29e4a2 100644 (file)
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -24,3 +24,5 @@ void amd_init_lfence(struct cpuinfo_x86 *c);
 void amd_init_ssbd(const struct cpuinfo_x86 *c);
 void amd_init_spectral_chicken(void);
 void detect_zen2_null_seg_behaviour(void);
+
+void intel_unlock_cpuid_leaves(struct cpuinfo_x86 *c);

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 2d439e0bd2fd54d4ca6c4b52554fccde46610b0a..490f7ff6f1fe51bf6844feee05b44cdd87e90ca0 100644 (file)
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -293,15 +293,11 @@ static void __init noinline intel_init_levelling(void)
                ctxt_switch_masking = intel_ctxt_switch_masking;
 }
 
-static void cf_check early_init_intel(struct cpuinfo_x86 *c)
+/* Unmask CPUID levels (and NX) if masked. */
+void intel_unlock_cpuid_leaves(struct cpuinfo_x86 *c)
 {
-       u64 misc_enable, disable;
-
-       /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
-       if (c->x86 == 15 && c->x86_cache_alignment == 64)
-               c->x86_cache_alignment = 128;
+       uint64_t misc_enable, disable;
 
-       /* Unmask CPUID levels and NX if masked: */
        rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 
        disable = misc_enable & (MSR_IA32_MISC_ENABLE_LIMIT_CPUID |
@@ -309,17 +305,26 @@ static void cf_check early_init_intel(struct cpuinfo_x86 *c)
        if (disable) {
                wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable);
                bootsym(trampoline_misc_enable_off) |= disable;
-               bootsym(trampoline_efer) |= EFER_NXE;
        }
-
-       if (disable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)
-               printk(KERN_INFO "revised cpuid level: %d\n",
-                      cpuid_eax(0));
+       if (disable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
+               c->cpuid_level = cpuid_eax(0);
+               printk(KERN_INFO "revised cpuid level: %u\n", c->cpuid_level);
+       }
        if (disable & MSR_IA32_MISC_ENABLE_XD_DISABLE) {
+               bootsym(trampoline_efer) |= EFER_NXE;
                write_efer(read_efer() | EFER_NXE);
                printk(KERN_INFO
                       "re-enabled NX (Execute Disable) protection\n");
        }
+}
+
+static void cf_check early_init_intel(struct cpuinfo_x86 *c)
+{
+       /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
+       if (c->x86 == 15 && c->x86_cache_alignment == 64)
+               c->x86_cache_alignment = 128;
+
+       intel_unlock_cpuid_leaves(c);
 
        /* CPUID workaround for Intel 0F33/0F34 CPU */
        if (boot_cpu_data.x86 == 0xF && boot_cpu_data.x86_model == 3 &&