nr_nodes = ((pci_conf_read32(0, 0, 0x18, 0x0, 0x60)>>4)&0x07)+1;
for (node = 0; node < nr_nodes; node++) {
/* PMM7: bus=0, dev=0x18+node, function=0x3, register=0x87. */
- pmm7 = pci_conf_read8(0, 0, 0x18+node, 0x3, 0x87);
+ pmm7 = pci_conf_read8(PCI_SBDF(0, 0, 0x18 + node, 3), 0x87);
/* Invalid read means we've updated every Northbridge. */
if (pmm7 == 0xFF)
break;
disp = vf * pdev->vf_rlen[bir];
limit = PCI_SRIOV_NUM_BARS;
}
- else switch ( pci_conf_read8(seg, bus, slot, func,
+ else switch ( pci_conf_read8(PCI_SBDF(seg, bus, slot, func),
PCI_HEADER_TYPE) & 0x7f )
{
case PCI_HEADER_TYPE_NORMAL:
#include <xen/pci.h>
#include <asm/io.h>
-#define PCI_CONF_ADDRESS(bus, dev, func, reg) \
- (0x80000000 | (bus << 16) | (dev << 11) | (func << 8) | (reg & ~3))
+#define PCI_CONF_ADDRESS(sbdf, reg) \
+ (0x80000000 | ((sbdf).bdf << 8) | ((reg) & ~3))
-uint8_t pci_conf_read8(
- unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func,
- unsigned int reg)
+uint8_t pci_conf_read8(pci_sbdf_t sbdf, unsigned int reg)
{
- u32 value;
+ uint32_t value;
- if ( seg || reg > 255 )
+ if ( sbdf.seg || reg > 255 )
{
- pci_mmcfg_read(seg, bus, PCI_DEVFN(dev, func), reg, 1, &value);
+ pci_mmcfg_read(sbdf.seg, sbdf.bus, sbdf.devfn, reg, 1, &value);
return value;
}
- else
- {
- BUG_ON((bus > 255) || (dev > 31) || (func > 7));
- return pci_conf_read(PCI_CONF_ADDRESS(bus, dev, func, reg), reg & 3, 1);
- }
+
+ return pci_conf_read(PCI_CONF_ADDRESS(sbdf, reg), reg & 3, 1);
}
+#undef PCI_CONF_ADDRESS
+#define PCI_CONF_ADDRESS(bus, dev, func, reg) \
+ (0x80000000 | (bus << 16) | (dev << 11) | (func << 8) | (reg & ~3))
+
uint16_t pci_conf_read16(
unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func,
unsigned int reg)
cap = __find_dbgp(bus, slot, func);
if ( !cap || ehci_num-- )
{
- if ( !func && !(pci_conf_read8(0, bus, slot, func,
+ if ( !func && !(pci_conf_read8(PCI_SBDF(0, bus, slot, func),
PCI_HEADER_TYPE) & 0x80) )
break;
continue;
offset = (debug_port >> 16) & 0xfff;
/* double check if the mem space is enabled */
- dbgp->pci_cr = pci_conf_read8(0, dbgp->bus, dbgp->slot, dbgp->func,
+ dbgp->pci_cr = pci_conf_read8(PCI_SBDF(0, dbgp->bus, dbgp->slot,
+ dbgp->func),
PCI_COMMAND);
if ( !(dbgp->pci_cr & PCI_COMMAND_MEMORY) )
{
uart->bar64 = bar_64;
uart->io_size = max(8U << param->reg_shift,
param->uart_offset);
- uart->irq = pci_conf_read8(0, b, d, f, PCI_INTERRUPT_PIN) ?
- pci_conf_read8(0, b, d, f, PCI_INTERRUPT_LINE) : 0;
+ uart->irq = pci_conf_read8(PCI_SBDF(0, b, d, f),
+ PCI_INTERRUPT_PIN) ?
+ pci_conf_read8(PCI_SBDF(0, b, d, f),
+ PCI_INTERRUPT_LINE) : 0;
return 0;
}
if (vendor_id != 0x1002 || dev_id != 0x4385)
continue;
- byte = pci_conf_read8(0, bus, 0x14, 0, 0xad);
+ byte = pci_conf_read8(PCI_SBDF(0, bus, 0x14, 0), 0xad);
if ( (byte >> 3) & 1 )
{
printk(XENLOG_WARNING "AMD-Vi: SP5100 erratum 28 detected, disabling IOMMU.\n"
}
}
- switch ( pci_conf_read8(seg, bus, dev, func, PCI_HEADER_TYPE) & 0x7f )
+ switch ( pci_conf_read8(pdev->sbdf, PCI_HEADER_TYPE) & 0x7f )
{
case PCI_HEADER_TYPE_BRIDGE:
if ( !bridge_ctl_mask )
case DEV_TYPE_PCIe2PCI_BRIDGE:
case DEV_TYPE_LEGACY_PCI_BRIDGE:
- sec_bus = pci_conf_read8(pseg->nr, bus, PCI_SLOT(devfn),
- PCI_FUNC(devfn), PCI_SECONDARY_BUS);
- sub_bus = pci_conf_read8(pseg->nr, bus, PCI_SLOT(devfn),
- PCI_FUNC(devfn), PCI_SUBORDINATE_BUS);
+ sec_bus = pci_conf_read8(pdev->sbdf, PCI_SECONDARY_BUS);
+ sub_bus = pci_conf_read8(pdev->sbdf, PCI_SUBORDINATE_BUS);
spin_lock(&pseg->bus2bridge_lock);
for ( ; sec_bus <= sub_bus; sec_bus++ )
/* update bus2bridge */
switch ( pdev->type )
{
- u8 dev, func, sec_bus, sub_bus;
+ uint8_t sec_bus, sub_bus;
case DEV_TYPE_PCIe2PCI_BRIDGE:
case DEV_TYPE_LEGACY_PCI_BRIDGE:
- dev = PCI_SLOT(pdev->devfn);
- func = PCI_FUNC(pdev->devfn);
- sec_bus = pci_conf_read8(pseg->nr, pdev->bus, dev, func,
- PCI_SECONDARY_BUS);
- sub_bus = pci_conf_read8(pseg->nr, pdev->bus, dev, func,
- PCI_SUBORDINATE_BUS);
+ sec_bus = pci_conf_read8(pdev->sbdf, PCI_SECONDARY_BUS);
+ sub_bus = pci_conf_read8(pdev->sbdf, PCI_SUBORDINATE_BUS);
spin_lock(&pseg->bus2bridge_lock);
for ( ; sec_bus <= sub_bus; sec_bus++ )
return -ENOMEM;
}
- if ( !func && !(pci_conf_read8(pseg->nr, bus, dev, func,
+ if ( !func && !(pci_conf_read8(PCI_SBDF(pseg->nr, bus, dev,
+ func),
PCI_HEADER_TYPE) & 0x80) )
break;
}
while ( --depth > 0 )
{
- bus = pci_conf_read8(seg, bus, path->dev, path->fn,
+ bus = pci_conf_read8(PCI_SBDF(seg, bus, path->dev, path->fn),
PCI_SECONDARY_BUS);
path++;
}
switch ( acpi_scope->entry_type )
{
case ACPI_DMAR_SCOPE_TYPE_BRIDGE:
- sec_bus = pci_conf_read8(seg, bus, path->dev, path->fn,
+ sec_bus = pci_conf_read8(PCI_SBDF(seg, bus, path->dev, path->fn),
PCI_SECONDARY_BUS);
- sub_bus = pci_conf_read8(seg, bus, path->dev, path->fn,
+ sub_bus = pci_conf_read8(PCI_SBDF(seg, bus, path->dev, path->fn),
PCI_SUBORDINATE_BUS);
if ( iommu_verbose )
printk(VTDPREFIX
if ( vid != 0x8086 )
return;
- did_hi = pci_conf_read8(0, 0, IGD_DEV, 0, 3);
- rid = pci_conf_read8(0, 0, IGD_DEV, 0, 8);
+ did_hi = pci_conf_read8(PCI_SBDF(0, 0, IGD_DEV, 0), 3);
+ rid = pci_conf_read8(PCI_SBDF(0, 0, IGD_DEV, 0), 8);
if ( (did_hi == 0x2A) && (rid == 0x7) )
is_cantiga_b3 = 1;
{
/* Match on System Management Registers on Device 20 Function 0 */
device = pci_conf_read32(0, bus, 20, 0, PCI_VENDOR_ID);
- rev = pci_conf_read8(0, bus, 20, 0, PCI_REVISION_ID);
+ rev = pci_conf_read8(PCI_SBDF(0, bus, 20, 0), PCI_REVISION_ID);
if ( rev == 0x13 && device == 0x342e8086 )
{
while ( max_cap-- )
{
- pos = pci_conf_read8(seg, bus, dev, func, pos);
+ pos = pci_conf_read8(PCI_SBDF(seg, bus, dev, func), pos);
if ( pos < 0x40 )
break;
pos &= ~3;
- id = pci_conf_read8(seg, bus, dev, func, pos + PCI_CAP_LIST_ID);
+ id = pci_conf_read8(PCI_SBDF(seg, bus, dev, func), pos + PCI_CAP_LIST_ID);
if ( id == 0xff )
break;
while ( ttl-- )
{
- pos = pci_conf_read8(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos);
+ pos = pci_conf_read8(PCI_SBDF3(seg, bus, devfn), pos);
if ( pos < 0x40 )
break;
pos &= ~3;
- id = pci_conf_read8(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn),
- pos + PCI_CAP_LIST_ID);
+ id = pci_conf_read8(PCI_SBDF3(seg, bus, devfn), pos + PCI_CAP_LIST_ID);
if ( id == 0xff )
break;
b = 0;
break;
case 1:
- switch ( pci_conf_read8(0, b, PCI_SLOT(df),
- PCI_FUNC(df),
+ switch ( pci_conf_read8(PCI_SBDF3(0, b, df),
PCI_HEADER_TYPE) )
{
case PCI_HEADER_TYPE_BRIDGE:
struct vpci_bar *bars = header->bars;
int rc;
- switch ( pci_conf_read8(pdev->seg, pdev->bus, slot, func, PCI_HEADER_TYPE)
- & 0x7f )
+ switch ( pci_conf_read8(pdev->sbdf, PCI_HEADER_TYPE) & 0x7f )
{
case PCI_HEADER_TYPE_NORMAL:
num_bars = PCI_HEADER_NORMAL_NR_BARS;
*/
if ( reg & 1 )
{
- data = pci_conf_read8(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn,
- reg);
+ data = pci_conf_read8(sbdf, reg);
data |= pci_conf_read16(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn,
reg + 1) << 8;
}
{
data = pci_conf_read16(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn,
reg);
- data |= pci_conf_read8(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn,
- reg + 2) << 16;
+ data |= pci_conf_read8(sbdf, reg + 2) << 16;
}
break;
break;
case 1:
- data = pci_conf_read8(sbdf.seg, sbdf.bus, sbdf.dev, sbdf.fn, reg);
+ data = pci_conf_read8(sbdf, reg);
break;
default:
int bus, int devfn);
void pci_check_disable_device(u16 seg, u8 bus, u8 devfn);
-uint8_t pci_conf_read8(
- unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func,
- unsigned int reg);
+uint8_t pci_conf_read8(pci_sbdf_t sbdf, unsigned int reg);
uint16_t pci_conf_read16(
unsigned int seg, unsigned int bus, unsigned int dev, unsigned int func,
unsigned int reg);