{
struct vcpu *v = current;
int i;
- const struct mmio_handler *mmio_handler;
+ const struct mmio_handler *mmio_handler = NULL;
const struct io_handler *io_handlers = &v->domain->arch.io_handlers;
for ( i = 0; i < io_handlers->num_entries; i++ )
if ( (info->gpa >= mmio_handler->addr) &&
(info->gpa < (mmio_handler->addr + mmio_handler->size)) )
- {
- return info->dabt.write ?
- mmio_handler->mmio_handler_ops->write_handler(v, info) :
- mmio_handler->mmio_handler_ops->read_handler(v, info);
- }
+ break;
}
- return 0;
+ if ( i == io_handlers->num_entries )
+ return 0;
+
+ if ( info->dabt.write )
+ return mmio_handler->mmio_handler_ops->write_handler(v, info,
+ mmio_handler->priv);
+ else
+ return mmio_handler->mmio_handler_ops->read_handler(v, info,
+ mmio_handler->priv);
}
void register_mmio_handler(struct domain *d,
const struct mmio_handler_ops *handle,
- paddr_t addr, paddr_t size)
+ paddr_t addr, paddr_t size, void *priv)
{
struct io_handler *handler = &d->arch.io_handlers;
handler->mmio_handlers[handler->num_entries].mmio_handler_ops = handle;
handler->mmio_handlers[handler->num_entries].addr = addr;
handler->mmio_handlers[handler->num_entries].size = size;
+ handler->mmio_handlers[handler->num_entries].priv = priv;
dsb(ish);
handler->num_entries++;
vgic_v2_hw.vbase = vbase;
}
-static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
+static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info,
+ void *priv)
{
struct hsr_dabt dabt = info->dabt;
struct cpu_user_regs *regs = guest_cpu_user_regs();
return vgic_to_sgi(v, sgir, sgi_mode, virq, &target);
}
-static int vgic_v2_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
+static int vgic_v2_distr_mmio_write(struct vcpu *v, mmio_info_t *info,
+ void *priv)
{
struct hsr_dabt dabt = info->dabt;
struct cpu_user_regs *regs = guest_cpu_user_regs();
sizeof(d->arch.vgic.shared_irqs[i].v2.itargets));
register_mmio_handler(d, &vgic_v2_distr_mmio_handler, d->arch.vgic.dbase,
- PAGE_SIZE);
+ PAGE_SIZE, NULL);
return 0;
}
return d->vcpu[vcpu_id];
}
-static int vgic_v3_rdistr_mmio_read(struct vcpu *v, mmio_info_t *info)
+static int vgic_v3_rdistr_mmio_read(struct vcpu *v, mmio_info_t *info,
+ void *priv)
{
uint32_t offset;
return 0;
}
-static int vgic_v3_rdistr_mmio_write(struct vcpu *v, mmio_info_t *info)
+static int vgic_v3_rdistr_mmio_write(struct vcpu *v, mmio_info_t *info,
+ void *priv)
{
uint32_t offset;
return 0;
}
-static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
+static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info,
+ void *priv)
{
struct hsr_dabt dabt = info->dabt;
struct cpu_user_regs *regs = guest_cpu_user_regs();
return 1;
}
-static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
+static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info,
+ void *priv)
{
struct hsr_dabt dabt = info->dabt;
struct cpu_user_regs *regs = guest_cpu_user_regs();
/* Register mmio handle for the Distributor */
register_mmio_handler(d, &vgic_distr_mmio_handler, d->arch.vgic.dbase,
- SZ_64K);
+ SZ_64K, NULL);
/*
* Register mmio handler per contiguous region occupied by the
for ( i = 0; i < d->arch.vgic.nr_regions; i++ )
register_mmio_handler(d, &vgic_rdistr_mmio_handler,
d->arch.vgic.rdist_regions[i].base,
- d->arch.vgic.rdist_regions[i].size);
+ d->arch.vgic.rdist_regions[i].size,
+ NULL);
d->arch.vgic.ctlr = VGICD_CTLR_DEFAULT;
#define domain_has_vuart(d) ((d)->arch.vuart.info != NULL)
-static int vuart_mmio_read(struct vcpu *v, mmio_info_t *info);
-static int vuart_mmio_write(struct vcpu *v, mmio_info_t *info);
+static int vuart_mmio_read(struct vcpu *v, mmio_info_t *info, void *priv);
+static int vuart_mmio_write(struct vcpu *v, mmio_info_t *info, void *priv);
static const struct mmio_handler_ops vuart_mmio_handler = {
.read_handler = vuart_mmio_read,
register_mmio_handler(d, &vuart_mmio_handler,
d->arch.vuart.info->base_addr,
- d->arch.vuart.info->size);
+ d->arch.vuart.info->size,
+ NULL);
return 0;
}
spin_unlock(&uart->lock);
}
-static int vuart_mmio_read(struct vcpu *v, mmio_info_t *info)
+static int vuart_mmio_read(struct vcpu *v, mmio_info_t *info, void *priv)
{
struct domain *d = v->domain;
struct hsr_dabt dabt = info->dabt;
return 1;
}
-static int vuart_mmio_write(struct vcpu *v, mmio_info_t *info)
+static int vuart_mmio_write(struct vcpu *v, mmio_info_t *info, void *priv)
{
struct domain *d = v->domain;
struct hsr_dabt dabt = info->dabt;
paddr_t gpa;
} mmio_info_t;
-typedef int (*mmio_read_t)(struct vcpu *v, mmio_info_t *info);
-typedef int (*mmio_write_t)(struct vcpu *v, mmio_info_t *info);
+typedef int (*mmio_read_t)(struct vcpu *v, mmio_info_t *info, void *priv);
+typedef int (*mmio_write_t)(struct vcpu *v, mmio_info_t *info, void *priv);
typedef int (*mmio_check_t)(struct vcpu *v, paddr_t addr);
struct mmio_handler_ops {
paddr_t addr;
paddr_t size;
const struct mmio_handler_ops *mmio_handler_ops;
+ void *priv;
};
struct io_handler {
extern int handle_mmio(mmio_info_t *info);
void register_mmio_handler(struct domain *d,
const struct mmio_handler_ops *handle,
- paddr_t addr, paddr_t size);
+ paddr_t addr, paddr_t size, void *priv);
int domain_io_init(struct domain *d);
#endif /* __ASM_ARM_MMIO_H__ */