Enable Px/Cx related CPUID/MSR bits for dom0 to get correct Px/Cx info.

Signed-off-by: Wei Gang <gang.wei@intel.com>

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 75997500bc0fb8bb6282f7177d651ec4caef9baa..ebdf25db4fa8e2e255e2b540d331ed64d22a4356 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -713,11 +713,13 @@ static int emulate_forced_invalid_op(struct cpu_user_regs *regs)
         __clear_bit(X86_FEATURE_PBE, &d);
 
         __clear_bit(X86_FEATURE_DTES64 % 32, &c);
-        __clear_bit(X86_FEATURE_MWAIT % 32, &c);
+        if ( !IS_PRIV(current->domain) )
+            __clear_bit(X86_FEATURE_MWAIT % 32, &c);
         __clear_bit(X86_FEATURE_DSCPL % 32, &c);
         __clear_bit(X86_FEATURE_VMXE % 32, &c);
         __clear_bit(X86_FEATURE_SMXE % 32, &c);
-        __clear_bit(X86_FEATURE_EST % 32, &c);
+        if ( !IS_PRIV(current->domain) )
+            __clear_bit(X86_FEATURE_EST % 32, &c);
         __clear_bit(X86_FEATURE_TM2 % 32, &c);
         if ( is_pv_32bit_vcpu(current) )
             __clear_bit(X86_FEATURE_CX16 % 32, &c);
@@ -2146,8 +2148,9 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
         case MSR_IA32_MISC_ENABLE:
             if ( rdmsr_safe(regs->ecx, regs->eax, regs->edx) )
                 goto fail;
-            regs->eax &= ~(MSR_IA32_MISC_ENABLE_PERF_AVAIL |
-                           MSR_IA32_MISC_ENABLE_MONITOR_ENABLE);
+            regs->eax &= ~MSR_IA32_MISC_ENABLE_PERF_AVAIL;
+            if ( !IS_PRIV(current->domain) )
+                regs->eax &= ~MSR_IA32_MISC_ENABLE_MONITOR_ENABLE;
             regs->eax |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL |
                          MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
                          MSR_IA32_MISC_ENABLE_XTPR_DISABLE;