]> xenbits.xensource.com Git - people/pauldu/qemu.git/commitdiff
riscv: hart: Add a "hartid-base" property to RISC-V hart array
authorBin Meng <bmeng.cn@gmail.com>
Fri, 6 Sep 2019 16:20:04 +0000 (09:20 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 17 Sep 2019 15:42:47 +0000 (08:42 -0700)
At present each hart's hartid in a RISC-V hart array is assigned
the same value of its index in the hart array. But for a system
that has multiple hart arrays, this is not the case any more.

Add a new "hartid-base" property so that hartid number can be
assigned based on the property value.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
hw/riscv/riscv_hart.c
include/hw/riscv/riscv_hart.h

index 6620e41cb7a843abe90572a830c3fbb94c435284..5b98227db6f20758f2978d55b72a2fe618b98b30 100644 (file)
@@ -29,6 +29,7 @@
 
 static Property riscv_harts_props[] = {
     DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
+    DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
     DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
     DEFINE_PROP_END_OF_LIST(),
 };
@@ -47,7 +48,7 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
     object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
                             sizeof(RISCVCPU), cpu_type,
                             &error_abort, NULL);
-    s->harts[idx].env.mhartid = idx;
+    s->harts[idx].env.mhartid = s->hartid_base + idx;
     qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
     object_property_set_bool(OBJECT(&s->harts[idx]), true,
                              "realized", &err);
index 3b52b50571d26ef408eb34e0fd1aebe45917b69c..c75856fa7386f74b33aee23dd7914a603b3d823b 100644 (file)
@@ -35,6 +35,7 @@ typedef struct RISCVHartArrayState {
 
     /*< public >*/
     uint32_t num_harts;
+    uint32_t hartid_base;
     char *cpu_type;
     RISCVCPU *harts;
 } RISCVHartArrayState;