x86: Build fixes and cleanups after Intel MCA changes.

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>

diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
index 1a95e3406f9075eae96de4a3b28a1a595f8c97a0..fb04a5b3ecad77520cac008cb4d83d0c893b4532 100644 (file)
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -256,7 +256,7 @@ static int fill_vmsr_data(int cpu, struct mcinfo_bank *mc_bank,
         d->arch.vmca_msrs.nr_injection++;
 
         printk(KERN_DEBUG "MCE: Found error @[CPU%d BANK%d "
-                "status %lx addr %lx domid %d]\n ",
+                "status %"PRIx64" addr %"PRIx64" domid %d]\n ",
                 entry->cpu, mc_bank->mc_bank,
                 mc_bank->mc_status, mc_bank->mc_addr, mc_bank->mc_domid);
     }
@@ -292,7 +292,7 @@ static int mce_actions(void) {
         if (mic == NULL) {
             printk(KERN_ERR "MCE: get local buffer entry failed\n ");
             ret = -1;
-                   goto end;
+            goto end;
         }
 
         mc_global = (struct mcinfo_global *)mic;
@@ -819,94 +819,97 @@ int intel_mce_wrmsr(u32 msr, u32 lo, u32 hi)
     struct domain *d = current->domain;
     struct bank_entry *entry = NULL;
     uint64_t value = (u64)hi << 32 | lo;
-    int ret = 0;
+    int ret = 1;
 
     spin_lock(&mce_locks);
     switch(msr)
     {
-        case MSR_IA32_MCG_CTL:
-            if (value != (u64)~0x0 && value != 0x0) {
-                printk(KERN_ERR "MCE: value writen to MCG_CTL"
-                    "should be all 0s or 1s\n");
-                ret = -1;
-                break;
-            }
-            if (!d || is_idle_domain(d)) {
-                printk(KERN_ERR "MCE: wrmsr not in DOM context, skip\n");
-                break;
-            }
-            d->arch.vmca_msrs.mcg_ctl = value;
+    case MSR_IA32_MCG_CTL:
+        if (value != (u64)~0x0 && value != 0x0) {
+            gdprintk(XENLOG_WARNING, "MCE: value writen to MCG_CTL"
+                     "should be all 0s or 1s\n");
+            ret = -1;
             break;
-        case MSR_IA32_MCG_STATUS:
-            if (!d || is_idle_domain(d)) {
-                printk(KERN_ERR "MCE: wrmsr not in DOM context, skip\n");
-                break;
-            }
-            d->arch.vmca_msrs.mcg_status = value;
-            printk(KERN_DEBUG "MCE: wrmsr MCG_CTL %lx\n", value);
+        }
+        if (!d || is_idle_domain(d)) {
+            gdprintk(XENLOG_WARNING, "MCE: wrmsr not in DOM context, skip\n");
             break;
-        case MSR_IA32_MC0_CTL2:
-        case MSR_IA32_MC1_CTL2:
-        case MSR_IA32_MC2_CTL2:
-        case MSR_IA32_MC3_CTL2:
-        case MSR_IA32_MC4_CTL2:
-        case MSR_IA32_MC5_CTL2:
-        case MSR_IA32_MC6_CTL2:
-        case MSR_IA32_MC7_CTL2:
-        case MSR_IA32_MC8_CTL2:
-            printk(KERN_ERR "We have disabled CMCI capability, "
-                    "Guest should not write this MSR!\n");
+        }
+        d->arch.vmca_msrs.mcg_ctl = value;
+        break;
+    case MSR_IA32_MCG_STATUS:
+        if (!d || is_idle_domain(d)) {
+            gdprintk(XENLOG_WARNING, "MCE: wrmsr not in DOM context, skip\n");
             break;
-        case MSR_IA32_MC0_CTL:
-        case MSR_IA32_MC1_CTL:
-        case MSR_IA32_MC2_CTL:
-        case MSR_IA32_MC3_CTL:
-        case MSR_IA32_MC4_CTL:
-        case MSR_IA32_MC5_CTL:
-        case MSR_IA32_MC6_CTL:
-        case MSR_IA32_MC7_CTL:
-        case MSR_IA32_MC8_CTL:
-            if (value != (u64)~0x0 && value != 0x0) {
-                printk(KERN_ERR "MCE: value writen to MCi_CTL"
-                    "should be all 0s or 1s\n");
-                ret = -1;
-                break;
-            }
-            if (!d || is_idle_domain(d)) {
-                printk(KERN_ERR "MCE: wrmsr not in DOM context, skip\n");
-                break;
-            }
-            d->arch.vmca_msrs.mci_ctl[(msr - MSR_IA32_MC0_CTL)/4] = value;
+        }
+        d->arch.vmca_msrs.mcg_status = value;
+        gdprintk(XENLOG_DEBUG, "MCE: wrmsr MCG_CTL %"PRIx64"\n", value);
+        break;
+    case MSR_IA32_MC0_CTL2:
+    case MSR_IA32_MC1_CTL2:
+    case MSR_IA32_MC2_CTL2:
+    case MSR_IA32_MC3_CTL2:
+    case MSR_IA32_MC4_CTL2:
+    case MSR_IA32_MC5_CTL2:
+    case MSR_IA32_MC6_CTL2:
+    case MSR_IA32_MC7_CTL2:
+    case MSR_IA32_MC8_CTL2:
+        gdprintk(XENLOG_WARNING, "We have disabled CMCI capability, "
+                 "Guest should not write this MSR!\n");
+        break;
+    case MSR_IA32_MC0_CTL:
+    case MSR_IA32_MC1_CTL:
+    case MSR_IA32_MC2_CTL:
+    case MSR_IA32_MC3_CTL:
+    case MSR_IA32_MC4_CTL:
+    case MSR_IA32_MC5_CTL:
+    case MSR_IA32_MC6_CTL:
+    case MSR_IA32_MC7_CTL:
+    case MSR_IA32_MC8_CTL:
+        if (value != (u64)~0x0 && value != 0x0) {
+            gdprintk(XENLOG_WARNING, "MCE: value writen to MCi_CTL"
+                     "should be all 0s or 1s\n");
+            ret = -1;
             break;
-        case MSR_IA32_MC0_STATUS:
-        case MSR_IA32_MC1_STATUS:
-        case MSR_IA32_MC2_STATUS:
-        case MSR_IA32_MC3_STATUS:
-        case MSR_IA32_MC4_STATUS:
-        case MSR_IA32_MC5_STATUS:
-        case MSR_IA32_MC6_STATUS:
-        case MSR_IA32_MC7_STATUS:
-        case MSR_IA32_MC8_STATUS:
-            if (!d || is_idle_domain(d)) {
-                /* Just skip */
-                printk(KERN_ERR "mce wrmsr: not in domain context!\n");
-                break;
-            }
-            /* Give the first entry of the list, it corresponds to current
-             * vMCE# injection. When vMCE# is finished processing by the
-             * the guest, this node will be deleted.
-             * Only error bank is written. Non-error bank simply return.
-             */
-            if ( !list_empty(&d->arch.vmca_msrs.impact_header) ) {
-                entry = list_entry(d->arch.vmca_msrs.impact_header.next,
-                    struct bank_entry, list);
-                if ( entry->bank == (msr - MSR_IA32_MC0_STATUS)/4 ) {
-                    entry->mci_status = value;
-                }
-                printk(KERN_DEBUG "MCE: wmrsr mci_status in vMCE# context\n");
-            }
-            printk(KERN_DEBUG "MCE: wrmsr mci_status val:%lx\n", value);
+        }
+        if (!d || is_idle_domain(d)) {
+            gdprintk(XENLOG_WARNING, "MCE: wrmsr not in DOM context, skip\n");
+            break;
+        }
+        d->arch.vmca_msrs.mci_ctl[(msr - MSR_IA32_MC0_CTL)/4] = value;
+        break;
+    case MSR_IA32_MC0_STATUS:
+    case MSR_IA32_MC1_STATUS:
+    case MSR_IA32_MC2_STATUS:
+    case MSR_IA32_MC3_STATUS:
+    case MSR_IA32_MC4_STATUS:
+    case MSR_IA32_MC5_STATUS:
+    case MSR_IA32_MC6_STATUS:
+    case MSR_IA32_MC7_STATUS:
+    case MSR_IA32_MC8_STATUS:
+        if (!d || is_idle_domain(d)) {
+            /* Just skip */
+            gdprintk(XENLOG_WARNING, "mce wrmsr: not in domain context!\n");
             break;
+        }
+        /* Give the first entry of the list, it corresponds to current
+         * vMCE# injection. When vMCE# is finished processing by the
+         * the guest, this node will be deleted.
+         * Only error bank is written. Non-error bank simply return.
+         */
+        if ( !list_empty(&d->arch.vmca_msrs.impact_header) ) {
+            entry = list_entry(d->arch.vmca_msrs.impact_header.next,
+                               struct bank_entry, list);
+            if ( entry->bank == (msr - MSR_IA32_MC0_STATUS)/4 ) {
+                entry->mci_status = value;
+            }
+            gdprintk(XENLOG_DEBUG, "MCE: wmrsr mci_status in vMCE# context\n");
+        }
+        gdprintk(XENLOG_DEBUG, "MCE: wrmsr mci_status val:%"PRIx64"\n", value);
+        break;
+    default:
+        ret = 0;
+        break;
     }
     spin_unlock(&mce_locks);
     return ret;
@@ -915,154 +918,155 @@ int intel_mce_wrmsr(u32 msr, u32 lo, u32 hi)
 int intel_mce_rdmsr(u32 msr, u32 *lo, u32 *hi)
 {
     struct domain *d = current->domain;
-    int ret = 0;
+    int ret = 1;
     struct bank_entry *entry = NULL;
 
     *lo = *hi = 0x0;
     spin_lock(&mce_locks);
     switch(msr)
     {
-        case MSR_IA32_MCG_STATUS:
-            if (!d || is_idle_domain(d)) {
-                printk(KERN_ERR "MCE: rdmsr not in domain context!\n");
-                *lo = *hi = 0x0;
-                break;
-            }
-            *lo = (u32)d->arch.vmca_msrs.mcg_status;
-            *hi = (u32)(d->arch.vmca_msrs.mcg_status >> 32);
-            printk(KERN_DEBUG "MCE: rd MCG_STATUS lo %x hi %x\n", *lo, *hi);
+    case MSR_IA32_MCG_STATUS:
+        if (!d || is_idle_domain(d)) {
+            gdprintk(XENLOG_WARNING, "MCE: rdmsr not in domain context!\n");
+            *lo = *hi = 0x0;
             break;
-        case MSR_IA32_MCG_CAP:
-            if (!d || is_idle_domain(d)) {
-                printk(KERN_ERR "MCE: rdmsr not in domain context!\n");
-                *lo = *hi = 0x0;
-                break;
-            }
-            *lo = (u32)d->arch.vmca_msrs.mcg_cap;
-            *hi = (u32)(d->arch.vmca_msrs.mcg_cap >> 32);
-            printk(KERN_DEBUG "MCE: rdmsr MCG_CAP lo %x hi %x\n", *lo, *hi);
+        }
+        *lo = (u32)d->arch.vmca_msrs.mcg_status;
+        *hi = (u32)(d->arch.vmca_msrs.mcg_status >> 32);
+        gdprintk(XENLOG_DEBUG, "MCE: rd MCG_STATUS lo %x hi %x\n", *lo, *hi);
+        break;
+    case MSR_IA32_MCG_CAP:
+        if (!d || is_idle_domain(d)) {
+            gdprintk(XENLOG_WARNING, "MCE: rdmsr not in domain context!\n");
+            *lo = *hi = 0x0;
             break;
-        case MSR_IA32_MCG_CTL:
-            if (!d || is_idle_domain(d)) {
-                printk(KERN_ERR "MCE: rdmsr not in domain context!\n");
-                *lo = *hi = 0x0;
-                break;
-            }
-            *lo = (u32)d->arch.vmca_msrs.mcg_ctl;
-            *hi = (u32)(d->arch.vmca_msrs.mcg_ctl >> 32);
-            printk(KERN_DEBUG "MCE: rdmsr MCG_CTL lo %x hi %x\n", *lo, *hi);
+        }
+        *lo = (u32)d->arch.vmca_msrs.mcg_cap;
+        *hi = (u32)(d->arch.vmca_msrs.mcg_cap >> 32);
+        gdprintk(XENLOG_DEBUG, "MCE: rdmsr MCG_CAP lo %x hi %x\n", *lo, *hi);
+        break;
+    case MSR_IA32_MCG_CTL:
+        if (!d || is_idle_domain(d)) {
+            gdprintk(XENLOG_WARNING, "MCE: rdmsr not in domain context!\n");
+            *lo = *hi = 0x0;
             break;
-        case MSR_IA32_MC0_CTL2:
-        case MSR_IA32_MC1_CTL2:
-        case MSR_IA32_MC2_CTL2:
-        case MSR_IA32_MC3_CTL2:
-        case MSR_IA32_MC4_CTL2:
-        case MSR_IA32_MC5_CTL2:
-        case MSR_IA32_MC6_CTL2:
-        case MSR_IA32_MC7_CTL2:
-        case MSR_IA32_MC8_CTL2:
-            printk(KERN_WARNING "We have disabled CMCI capability, "
-                    "Guest should not read this MSR!\n");
+        }
+        *lo = (u32)d->arch.vmca_msrs.mcg_ctl;
+        *hi = (u32)(d->arch.vmca_msrs.mcg_ctl >> 32);
+        gdprintk(XENLOG_DEBUG, "MCE: rdmsr MCG_CTL lo %x hi %x\n", *lo, *hi);
+        break;
+    case MSR_IA32_MC0_CTL2:
+    case MSR_IA32_MC1_CTL2:
+    case MSR_IA32_MC2_CTL2:
+    case MSR_IA32_MC3_CTL2:
+    case MSR_IA32_MC4_CTL2:
+    case MSR_IA32_MC5_CTL2:
+    case MSR_IA32_MC6_CTL2:
+    case MSR_IA32_MC7_CTL2:
+    case MSR_IA32_MC8_CTL2:
+        gdprintk(XENLOG_WARNING, "We have disabled CMCI capability, "
+                 "Guest should not read this MSR!\n");
+        break;
+    case MSR_IA32_MC0_CTL:
+    case MSR_IA32_MC1_CTL:
+    case MSR_IA32_MC2_CTL:
+    case MSR_IA32_MC3_CTL:
+    case MSR_IA32_MC4_CTL:
+    case MSR_IA32_MC5_CTL:
+    case MSR_IA32_MC6_CTL:
+    case MSR_IA32_MC7_CTL:
+    case MSR_IA32_MC8_CTL:
+        if (!d || is_idle_domain(d)) {
+            gdprintk(XENLOG_WARNING, "MCE: rdmsr not in domain context!\n");
+            *lo = *hi = 0x0;
             break;
-        case MSR_IA32_MC0_CTL:
-        case MSR_IA32_MC1_CTL:
-        case MSR_IA32_MC2_CTL:
-        case MSR_IA32_MC3_CTL:
-        case MSR_IA32_MC4_CTL:
-        case MSR_IA32_MC5_CTL:
-        case MSR_IA32_MC6_CTL:
-        case MSR_IA32_MC7_CTL:
-        case MSR_IA32_MC8_CTL:
-            if (!d || is_idle_domain(d)) {
-                printk(KERN_ERR "MCE: rdmsr not in domain context!\n");
-                *lo = *hi = 0x0;
-                break;
-            }
-            *lo = (u32)d->arch.vmca_msrs.mci_ctl[(msr - MSR_IA32_MC0_CTL)/4];
-            *hi =
-                (u32)(d->arch.vmca_msrs.mci_ctl[(msr - MSR_IA32_MC0_CTL)/4]
-                    >> 32);
-            printk(KERN_DEBUG "MCE: rdmsr MCi_CTL lo %x hi %x\n", *lo, *hi);
+        }
+        *lo = (u32)d->arch.vmca_msrs.mci_ctl[(msr - MSR_IA32_MC0_CTL)/4];
+        *hi =
+            (u32)(d->arch.vmca_msrs.mci_ctl[(msr - MSR_IA32_MC0_CTL)/4]
+                  >> 32);
+        gdprintk(XENLOG_DEBUG, "MCE: rdmsr MCi_CTL lo %x hi %x\n", *lo, *hi);
+        break;
+    case MSR_IA32_MC0_STATUS:
+    case MSR_IA32_MC1_STATUS:
+    case MSR_IA32_MC2_STATUS:
+    case MSR_IA32_MC3_STATUS:
+    case MSR_IA32_MC4_STATUS:
+    case MSR_IA32_MC5_STATUS:
+    case MSR_IA32_MC6_STATUS:
+    case MSR_IA32_MC7_STATUS:
+    case MSR_IA32_MC8_STATUS:
+        /* Only error bank is read. Non-error bank simply return */
+        *lo = *hi = 0x0;
+        gdprintk(XENLOG_DEBUG, "MCE: rdmsr mci_status\n");
+        if (!d || is_idle_domain(d)) {
+            gdprintk(XENLOG_WARNING, "mce_rdmsr: not in domain context!\n");
             break;
-        case MSR_IA32_MC0_STATUS:
-        case MSR_IA32_MC1_STATUS:
-        case MSR_IA32_MC2_STATUS:
-        case MSR_IA32_MC3_STATUS:
-        case MSR_IA32_MC4_STATUS:
-        case MSR_IA32_MC5_STATUS:
-        case MSR_IA32_MC6_STATUS:
-        case MSR_IA32_MC7_STATUS:
-        case MSR_IA32_MC8_STATUS:
-            /* Only error bank is read. Non-error bank simply return */
-            *lo = *hi = 0x0;
-            printk(KERN_DEBUG "MCE: rdmsr mci_status\n");
-            if (!d || is_idle_domain(d)) {
-                printk(KERN_ERR "mce_rdmsr: not in domain context!\n");
-                break;
-            }
-            if (!list_empty(&d->arch.vmca_msrs.impact_header)) {
-                entry = list_entry(d->arch.vmca_msrs.impact_header.next,
-                    struct bank_entry, list);
-                if ( entry->bank == (msr - MSR_IA32_MC0_STATUS)/4 ) {
-                    *lo = entry->mci_status;
-                    *hi = entry->mci_status >> 32;
-                    printk(KERN_DEBUG "MCE: rdmsr MCi_STATUS in vmCE# context "
-                        "lo %x hi %x\n", *lo, *hi);
-                }
+        }
+        if (!list_empty(&d->arch.vmca_msrs.impact_header)) {
+            entry = list_entry(d->arch.vmca_msrs.impact_header.next,
+                               struct bank_entry, list);
+            if ( entry->bank == (msr - MSR_IA32_MC0_STATUS)/4 ) {
+                *lo = entry->mci_status;
+                *hi = entry->mci_status >> 32;
+                gdprintk(XENLOG_DEBUG, "MCE: rdmsr MCi_STATUS in vmCE# context "
+                         "lo %x hi %x\n", *lo, *hi);
             }
+        }
+        break;
+    case MSR_IA32_MC0_ADDR:
+    case MSR_IA32_MC1_ADDR:
+    case MSR_IA32_MC2_ADDR:
+    case MSR_IA32_MC3_ADDR:
+    case MSR_IA32_MC4_ADDR:
+    case MSR_IA32_MC5_ADDR:
+    case MSR_IA32_MC6_ADDR:
+    case MSR_IA32_MC7_ADDR:
+    case MSR_IA32_MC8_ADDR:
+        *lo = *hi = 0x0;
+        if (!d || is_idle_domain(d)) {
+            gdprintk(XENLOG_WARNING, "mce_rdmsr: not in domain context!\n");
             break;
-        case MSR_IA32_MC0_ADDR:
-        case MSR_IA32_MC1_ADDR:
-        case MSR_IA32_MC2_ADDR:
-        case MSR_IA32_MC3_ADDR:
-        case MSR_IA32_MC4_ADDR:
-        case MSR_IA32_MC5_ADDR:
-        case MSR_IA32_MC6_ADDR:
-        case MSR_IA32_MC7_ADDR:
-        case MSR_IA32_MC8_ADDR:
-            *lo = *hi = 0x0;
-            if (!d || is_idle_domain(d)) {
-                printk(KERN_ERR "mce_rdmsr: not in domain context!\n");
-                break;
-            }
-            if (!list_empty(&d->arch.vmca_msrs.impact_header)) {
-                entry = list_entry(d->arch.vmca_msrs.impact_header.next,
-                    struct bank_entry, list);
-                if ( entry->bank == (msr - MSR_IA32_MC0_ADDR)/4 ) {
-                    *lo = entry->mci_addr;
-                    *hi = entry->mci_addr >> 32;
-                    printk(KERN_DEBUG "MCE: rdmsr MCi_ADDR in vMCE# context "
-                        "lo %x hi %x\n", *lo, *hi);
-                }
+        }
+        if (!list_empty(&d->arch.vmca_msrs.impact_header)) {
+            entry = list_entry(d->arch.vmca_msrs.impact_header.next,
+                               struct bank_entry, list);
+            if ( entry->bank == (msr - MSR_IA32_MC0_ADDR)/4 ) {
+                *lo = entry->mci_addr;
+                *hi = entry->mci_addr >> 32;
+                gdprintk(XENLOG_DEBUG, "MCE: rdmsr MCi_ADDR in vMCE# context "
+                         "lo %x hi %x\n", *lo, *hi);
             }
+        }
+        break;
+    case MSR_IA32_MC0_MISC:
+    case MSR_IA32_MC1_MISC:
+    case MSR_IA32_MC2_MISC:
+    case MSR_IA32_MC3_MISC:
+    case MSR_IA32_MC4_MISC:
+    case MSR_IA32_MC5_MISC:
+    case MSR_IA32_MC6_MISC:
+    case MSR_IA32_MC7_MISC:
+    case MSR_IA32_MC8_MISC:
+        *lo = *hi = 0x0;
+        if (!d || is_idle_domain(d)) {
+            gdprintk(XENLOG_WARNING, "MCE: rdmsr not in domain context!\n");
             break;
-        case MSR_IA32_MC0_MISC:
-        case MSR_IA32_MC1_MISC:
-        case MSR_IA32_MC2_MISC:
-        case MSR_IA32_MC3_MISC:
-        case MSR_IA32_MC4_MISC:
-        case MSR_IA32_MC5_MISC:
-        case MSR_IA32_MC6_MISC:
-        case MSR_IA32_MC7_MISC:
-        case MSR_IA32_MC8_MISC:
-            *lo = *hi = 0x0;
-            if (!d || is_idle_domain(d)) {
-                printk(KERN_ERR "MCE: rdmsr not in domain context!\n");
-                break;
-            }
-            if (!list_empty(&d->arch.vmca_msrs.impact_header)) {
-                entry = list_entry(d->arch.vmca_msrs.impact_header.next,
-                    struct bank_entry, list);
-                if ( entry->bank == (msr - MSR_IA32_MC0_MISC)/4 ) {
-                    *lo = entry->mci_misc;
-                    *hi = entry->mci_misc >> 32;
-                    printk(KERN_DEBUG "MCE: rdmsr MCi_MISC in vMCE# context "
-                        " lo %x hi %x\n", *lo, *hi);
-                }
+        }
+        if (!list_empty(&d->arch.vmca_msrs.impact_header)) {
+            entry = list_entry(d->arch.vmca_msrs.impact_header.next,
+                               struct bank_entry, list);
+            if ( entry->bank == (msr - MSR_IA32_MC0_MISC)/4 ) {
+                *lo = entry->mci_misc;
+                *hi = entry->mci_misc >> 32;
+                gdprintk(XENLOG_DEBUG, "MCE: rdmsr MCi_MISC in vMCE# context "
+                         " lo %x hi %x\n", *lo, *hi);
             }
-            break;
-        default:
-            break;
+        }
+        break;
+    default:
+        ret = 0;
+        break;
     }
     spin_unlock(&mce_locks);
     return ret;

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index cdbb0868544b81c74a7cfde53a18ed1b64c84f1e..dfdc7bf044bbcfa48787accb3565f19c1197762f 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2208,13 +2208,13 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
         default:
             if ( wrmsr_hypervisor_regs(regs->ecx, eax, edx) )
                 break;
-            if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
-                if ( intel_mce_wrmsr(regs->ecx, eax, edx) != 0) {
-                    gdprintk(XENLOG_ERR, "MCE: vMCE MSRS(%lx) Write"
-                        " (%x:%x) Fails! ", regs->ecx, edx, eax);
+            if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+            {
+                int rc = intel_mce_wrmsr(regs->ecx, eax, edx);
+                if ( rc == -1 )
                     goto fail;
-                }
-                break;
+                if ( rc == 0 )
+                    break;
             }
 
             if ( (rdmsr_safe(regs->ecx, l, h) != 0) ||
@@ -2301,9 +2301,13 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
             if ( rdmsr_safe(regs->ecx, regs->eax, regs->edx) )
                 goto fail;
 
-            if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
-                if ( intel_mce_rdmsr(regs->ecx, &eax, &edx) != 0)
-                    printk(KERN_ERR "MCE: Not MCE MSRs %lx\n", regs->ecx);
+            if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+            {
+                int rc = intel_mce_rdmsr(regs->ecx, &eax, &edx);
+                if ( rc == -1 )
+                    goto fail;
+                if ( rc == 0 )
+                    break;
             }
 
             break;