/* Signal whether the ACPI C1E quirk is required. */
bool __read_mostly amd_acpi_c1e_quirk;
bool __ro_after_init amd_legacy_ssbd;
+bool __initdata amd_virt_spec_ctrl;
static inline int rdmsr_amd_safe(unsigned int msr, unsigned int *lo,
unsigned int *hi)
#include <xen/param.h>
#include <xen/sched.h>
#include <xen/nospec.h>
+#include <asm/amd.h>
#include <asm/cpuid.h>
#include <asm/hvm/hvm.h>
#include <asm/hvm/nestedhvm.h>
/*
* VIRT_SSBD is exposed in the default policy as a result of
- * VIRT_SC_MSR_HVM being set, it also needs exposing in the max policy.
+ * amd_virt_spec_ctrl being set, it also needs exposing in the max policy.
*/
- if ( boot_cpu_has(X86_FEATURE_VIRT_SC_MSR_HVM) )
+ if ( amd_virt_spec_ctrl )
__set_bit(X86_FEATURE_VIRT_SSBD, hvm_featureset);
/*
/*
* Only expose VIRT_SSBD if AMD_SSBD is not available, and thus
- * VIRT_SC_MSR_HVM is set.
+ * amd_virt_spec_ctrl is set.
*/
- if ( boot_cpu_has(X86_FEATURE_VIRT_SC_MSR_HVM) )
+ if ( amd_virt_spec_ctrl )
__set_bit(X86_FEATURE_VIRT_SSBD, hvm_featureset);
sanitise_featureset(hvm_featureset);
void amd_check_disable_c1e(unsigned int port, u8 value);
extern bool amd_legacy_ssbd;
+extern bool amd_virt_spec_ctrl;
bool amd_setup_legacy_ssbd(void);
void amd_set_legacy_ssbd(bool enable);
XEN_CPUFEATURE(MFENCE_RDTSC, X86_SYNTH( 9)) /* MFENCE synchronizes RDTSC */
XEN_CPUFEATURE(XEN_SMEP, X86_SYNTH(10)) /* SMEP gets used by Xen itself */
XEN_CPUFEATURE(XEN_SMAP, X86_SYNTH(11)) /* SMAP gets used by Xen itself */
-XEN_CPUFEATURE(VIRT_SC_MSR_HVM, X86_SYNTH(12)) /* MSR_VIRT_SPEC_CTRL exposed to HVM */
+/* Bit 12 unused. */
XEN_CPUFEATURE(IND_THUNK_LFENCE, X86_SYNTH(13)) /* Use IND_THUNK_LFENCE */
XEN_CPUFEATURE(IND_THUNK_JMP, X86_SYNTH(14)) /* Use IND_THUNK_JMP */
XEN_CPUFEATURE(SC_NO_BRANCH_HARDEN, X86_SYNTH(15)) /* (Disable) Conditional branch hardening */
(boot_cpu_has(X86_FEATURE_SC_MSR_HVM) ||
boot_cpu_has(X86_FEATURE_SC_RSB_HVM) ||
boot_cpu_has(X86_FEATURE_IBPB_ENTRY_HVM) ||
- boot_cpu_has(X86_FEATURE_VIRT_SC_MSR_HVM) ||
+ amd_virt_spec_ctrl ||
opt_eager_fpu || opt_md_clear_hvm) ? "" : " None",
boot_cpu_has(X86_FEATURE_SC_MSR_HVM) ? " MSR_SPEC_CTRL" : "",
(boot_cpu_has(X86_FEATURE_SC_MSR_HVM) ||
- boot_cpu_has(X86_FEATURE_VIRT_SC_MSR_HVM)) ? " MSR_VIRT_SPEC_CTRL"
- : "",
+ amd_virt_spec_ctrl) ? " MSR_VIRT_SPEC_CTRL" : "",
boot_cpu_has(X86_FEATURE_SC_RSB_HVM) ? " RSB" : "",
opt_eager_fpu ? " EAGER_FPU" : "",
opt_md_clear_hvm ? " MD_CLEAR" : "",
/* Support VIRT_SPEC_CTRL.SSBD if AMD_SSBD is not available. */
if ( opt_msr_sc_hvm && !cpu_has_amd_ssbd &&
(cpu_has_virt_ssbd || (amd_legacy_ssbd && amd_setup_legacy_ssbd())) )
- setup_force_cpu_cap(X86_FEATURE_VIRT_SC_MSR_HVM);
+ amd_virt_spec_ctrl = true;
/* Figure out default_xen_spec_ctrl. */
if ( has_spec_ctrl && ibrs )