int dcache_line_size = env->dcache_line_size;
/* XXX: should be 970 specific (?) */
- if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
+ if (((env->spr[SPR_970_HID5] >> 6) & 0x3) == 0x2)
dcache_line_size = 32;
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_970_HID5, "HID5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+#if defined(CONFIG_USER_ONLY)
+ 0x00000080
+#else
+ 0x00000000
+#endif
+ );
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);
spr_register(env, SPR_970_HID5, "HID5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
- 0x00000000);
+#if defined(CONFIG_USER_ONLY)
+ 0x00000080
+#else
+ 0x00000000
+#endif
+ );
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);
spr_register(env, SPR_970_HID5, "HID5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
- 0x00000000);
+#if defined(CONFIG_USER_ONLY)
+ 0x00000080
+#else
+ 0x00000000
+#endif
+ );
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);