OvmfPkg/PlatformInitLib: simplify mtrr setup

With the new mmconfig location at 0xe0000000 above the 32-bit PCI MMIO
window we don't have to special-case the mmconfig xbar any more.  We'll
just add a mtrr uncachable entry starting at MMIO window base and ending
at 4GB.

Update comments to match reality.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>

diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
index 38cece9173e8011fd1930d43e163cd3048b24198..f85a63ac51307a2f7b59e314f7885dba78231663 100644 (file)
--- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c
+++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
@@ -61,33 +61,20 @@ PlatformQemuUc32BaseInitialization (
     return;\r
   }\r
 \r
+  ASSERT (\r
+    PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID ||\r
+    PlatformInfoHob->HostBridgeDevId == INTEL_82441_DEVICE_ID\r
+    );\r
+\r
   PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);\r
 \r
   if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
     ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);\r
     ASSERT (PcdGet64 (PcdPciExpressBaseAddress) >= PlatformInfoHob->LowMemory);\r
-\r
-    if (PlatformInfoHob->LowMemory <= BASE_2GB) {\r
-      // Newer qemu with gigabyte aligned memory,\r
-      // 32-bit pci mmio window is 2G -> 4G then.\r
-      PlatformInfoHob->Uc32Base = BASE_2GB;\r
-    } else {\r
-      //\r
-      // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,\r
-      // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for\r
-      // setting PcdPciExpressBaseAddress such that describing the\r
-      // [PcdPciExpressBaseAddress, 4GB) range require a very small number of\r
-      // variable MTRRs (preferably 1 or 2).\r
-      //\r
-      PlatformInfoHob->Uc32Base = (UINT32)PcdGet64 (PcdPciExpressBaseAddress);\r
-    }\r
-\r
-    return;\r
   }\r
 \r
-  ASSERT (PlatformInfoHob->HostBridgeDevId == INTEL_82441_DEVICE_ID);\r
   //\r
-  // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one\r
+  // Start with the [LowerMemorySize, 4GB) range. Make sure one\r
   // variable MTRR suffices by truncating the size to a whole power of two,\r
   // while keeping the end affixed to 4GB. This will round the base up.\r
   //\r
@@ -1027,6 +1014,13 @@ PlatformQemuInitializeRam (
   // practically any alignment, and we may not have enough variable MTRRs to\r
   // cover it exactly.\r
   //\r
+  // Because of that PlatformQemuUc32BaseInitialization() will round\r
+  // up PlatformInfoHob->LowMemory to make sure a single mtrr register\r
+  // is enough.  The the result will be stored in\r
+  // PlatformInfoHob->Uc32Base.  On a typical qemu configuration with\r
+  // gigabyte-alignment being used LowMemory will be 2 or 3 GB and no\r
+  // rounding is needed, so LowMemory and Uc32Base will be identical.\r
+  //\r
   if (IsMtrrSupported () && (PlatformInfoHob->HostBridgeDevId != CLOUDHV_DEVICE_ID)) {\r
     MtrrGetAllMtrrs (&MtrrSettings);\r
 \r
@@ -1056,8 +1050,8 @@ PlatformQemuInitializeRam (
     ASSERT_EFI_ERROR (Status);\r
 \r
     //\r
-    // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI\r
-    // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.\r
+    // Set the memory range from the start of the 32-bit PCI MMIO\r
+    // aperture to 4GB as uncacheable.\r
     //\r
     Status = MtrrSetMemoryAttribute (\r
                PlatformInfoHob->Uc32Base,\r