Avoid redundant TLB flushes (Daniel Jacobowitz).

diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index bf397c9b44345590f90e6ba2a79b53fd1ff6d7e4..6e31436f5ba77c73023cfeeec0c205433617f1c8 100644 (file)
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -572,8 +572,17 @@ static void invalidate_tlb (int idx)
 {
     tlb_t *tlb;
     target_ulong addr;
+    uint8_t ASID;
+
+    ASID = env->CP0_EntryHi & 0xFF;
 
     tlb = &env->tlb[idx];
+    /* The qemu TLB is flushed then the ASID changes, so no need to
+       flush these entries again.  */
+    if (tlb->G == 0 && tlb->ASID != ASID) {
+        return;
+    }
+
     if (tlb->V0) {
         tb_invalidate_page_range(tlb->PFN[0], tlb->end - tlb->VPN);
         addr = tlb->VPN;