Although the "Intel Virtualization Technology FlexMigration

Application Note" (http://www.intel.com/Assets/PDF/manual/323850.pdf)
does not document support for extended model 2H model DH (Intel Xeon
Processor E5 Family), empirical evidence shows that the same MSR
addresses can be used for cpuid masking as exdended model 2H model AH
(Intel Xen Processor E3-1200 Family).

Signed-off-by: Matt Wilson <msw@amazon.com>
Acked-by: Nakajima, Jun <jun.nakajima@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 5633c078544865b583ee5809716e2216cb4779a7..f26936ae378c9c97a698e4d2914a3244be5a7589 100644 (file)
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -104,7 +104,7 @@ static void __devinit set_cpuidmask(const struct cpuinfo_x86 *c)
                        return;
                extra = "xsave ";
                break;
-       case 0x2a:
+       case 0x2a: case 0x2d:
                wrmsr(MSR_INTEL_CPUID1_FEATURE_MASK_V2,
                      opt_cpuid_mask_ecx,
                      opt_cpuid_mask_edx);