arndale: Add serial debugcode in head.S.

TODO: Having platform specific macro here would be greate.

diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index 20e9da6228ad69b1597257b4488bd82b7c22d21c..c327a4498dc0ca791f01c67e3d5d4024d2e3fffc 100644 (file)
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -348,9 +348,11 @@ fail:   PRINT("- Boot failed -\r\n")
 
 #ifdef EARLY_UART_ADDRESS
 
-/* Bring up the UART. Specific to the PL011 UART.
+/* Bring up the UART.
  * Clobbers r0-r2 */
 init_uart:
+#ifdef MACH_VEXPRESS
+        /* Specific to the PL011 UART. */
         mov   r1, #0x0
         str   r1, [r11, #0x28]       /* -> UARTFBRD (Baud divisor fraction) */
         mov   r1, #0x4               /* 7.3728MHz / 0x4 == 16 * 115200 */
@@ -359,22 +361,60 @@ init_uart:
         str   r1, [r11, #0x2C]       /* -> UARTLCR_H (Line control) */
         ldr   r1, =0x00000301        /* RXE | TXE | UARTEN */
         str   r1, [r11, #0x30]       /* -> UARTCR (Control Register) */
+#elif defined MACH_EXYNOS5
+        /* Specific to the EXYNOS5 UART. */
+        /* init clock */
+        ldr   r1, =0x10020000
+        /* select MPLL (800MHz) source clock */
+        ldr   r0, [r1, #0x250]
+        and   r0, r0, #(~(0xf<<8))
+        orr   r0, r0, #(0x6<<8)
+        str   r0, [r1, #0x250]
+        /* ration 800/(7+1) */
+        ldr   r0, [r1, #0x558]
+        and   r0, r0, #(~(0xf<<8))
+        orr   r0, r0, #(0x7<<8)
+        str   r0, [r1, #0x558]
+
+        mov   r1, #4
+        str   r1, [r11, #0x2c]          /* -> UARTIBRD (Baud divisor fraction) */
+        mov   r1, #53
+        str   r1, [r11, #0x28]          /* -> UARTIBRD (Baud divisor integer) */
+        mov   r1, #3                    /* 8n1 */
+        str   r1, [r11, #0x0]           /* -> (Line control) */
+        ldr   r1, =(1<<2)               /* TX IRQMODE */
+        str   r1, [r11, #0x4]           /* -> (Control Register) */
+        mov   r1, #0x0
+        str   r1, [r11, #0x8]           /* disable FIFO */
+        mov   r1, #0x0
+        str   r1, [r11, #0x0C]          /* no auto flow control */
+#endif
         adr   r0, 1f
         b     puts
 1:      .asciz "- UART enabled -\r\n"
         .align 4
 
-/* Print early debug messages.  Specific to the PL011 UART.
+/* Print early debug messages.
  * r0: Nul-terminated string to print.
  * Clobbers r0-r2 */
 puts:
+#ifdef MACH_VEXPRESS
         ldr   r2, [r11, #0x18]       /* <- UARTFR (Flag register) */
         tst   r2, #0x8               /* Check BUSY bit */
         bne   puts                   /* Wait for the UART to be ready */
+#elif defined MACH_EXYNOS5
+        ldr   r2, [r11, #0x10]       /* <- UTRSTAT (Flag register) */
+        tst   r2, #(1<<1)            /* Check BUSY bit */
+        beq   puts                   /* Wait for the UART to be ready */
+#endif
         ldrb  r2, [r0], #1           /* Load next char */
         teq   r2, #0                 /* Exit on nul */
         moveq pc, lr
+#ifdef MACH_VEXPRESS
         str   r2, [r11]              /* -> UARTDR (Data Register) */
+#elif defined MACH_EXYNOS5
+        str   r2, [r11, #0x20]       /* -> UTXH (Data Register) */
+#endif
         b     puts
 
 /* Print a 32-bit number in hex.  Specific to the PL011 UART.
@@ -383,12 +423,22 @@ puts:
 putn:
         adr   r1, hex
         mov   r3, #8
+#ifdef MACH_VEXPRESS
 1:      ldr   r2, [r11, #0x18]       /* <- UARTFR (Flag register) */
         tst   r2, #0x8               /* Check BUSY bit */
         bne   1b                     /* Wait for the UART to be ready */
+#elif defined MACH_EXYNOS5
+1:      ldr   r2, [r11, #0x10]       /* <- UTRSTAT (Flag register) */
+        tst   r2, #(1<<1)            /* Check BUSY bit */
+        beq   1b                     /* Wait for the UART to be ready */
+#endif
         and   r2, r0, #0xf0000000    /* Mask off the top nybble */
         ldrb  r2, [r1, r2, lsr #28]  /* Convert to a char */
+#ifdef MACH_VEXPRESS
         str   r2, [r11]              /* -> UARTDR (Data Register) */
+#elif defined MACH_EXYNOS5
+        str   r2, [r11, #0x20]       /* -> UTXH (Data Register) */
+#endif
         lsl   r0, #4                 /* Roll it through one nybble at a time */
         subs  r3, r3, #1
         bne   1b

diff --git a/xen/include/asm-arm/config.h b/xen/include/asm-arm/config.h
index 51b6627e620d5adc8a432e83e0933a0b72f9219a..ccad343aa571f9eb997ebd2889c1af8545b673ca 100644 (file)
--- a/xen/include/asm-arm/config.h
+++ b/xen/include/asm-arm/config.h
@@ -113,8 +113,13 @@ extern unsigned long frametable_virt_end;
 #define watchdog_disable() ((void)0)
 #define watchdog_enable()  ((void)0)
 
+#define MACH_EXYNOS5
 /* Board-specific: base address of PL011 UART */
-#define EARLY_UART_ADDRESS 0x1c090000
+#ifdef MACH_VEXPRESS
+# define EARLY_UART_ADDRESS 0x1c090000
+#elif defined MACH_EXYNOS5
+# define EARLY_UART_ADDRESS 0x12c20000
+#endif
 /* Board-specific: base address of GIC + its regs */
 #define GIC_BASE_ADDRESS 0x10480000
 #define GIC_DR_OFFSET 0x1000