platform: zynqmp: rename reset node macros

To maintain future compatibility, rename reset node macros to have
PM_RST_* prefix instead of previously used PM_RESET_* prefix.

Signed-off-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@xilinx.com>
Signed-off-by: Stefano Stabellini <stefano.stabellini@xilinx.com>
Reviewed-by: Stefano Stabellini <stefano.stabellini@xilinx.com>

diff --git a/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c b/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c
index f7ecb9d450296b6d8a512d4086bfdf7d9e103307..d1ef6462a48580ca6bb12851f3e7eedbf9cb814b 100644 (file)
--- a/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c
+++ b/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c
@@ -178,132 +178,132 @@ static const struct pm_access pm_node_access[] = {
  * over the affected node to grant it access to EEMI calls for
  * resetting that node.
  */
-#define PM_RESET_IDX(n) (n - PM_RESET_PCIE_CFG)
+#define PM_RESET_IDX(n) (n - PM_RST_PCIE_CFG)
 static const struct pm_access pm_reset_access[] = {
-    [PM_RESET_IDX(PM_RESET_PCIE_CFG)] = { MM_AXIPCIE_MAIN },
-    [PM_RESET_IDX(PM_RESET_PCIE_BRIDGE)] = { MM_PCIE_ATTRIB },
-    [PM_RESET_IDX(PM_RESET_PCIE_CTRL)] = { MM_PCIE_ATTRIB },
-
-    [PM_RESET_IDX(PM_RESET_DP)] = { MM_DP },
-    [PM_RESET_IDX(PM_RESET_SWDT_CRF)] = { MM_SWDT },
-    [PM_RESET_IDX(PM_RESET_AFI_FM5)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_AFI_FM4)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_AFI_FM3)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_AFI_FM2)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_AFI_FM1)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_AFI_FM0)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_PCIE_CFG)] = { MM_AXIPCIE_MAIN },
+    [PM_RESET_IDX(PM_RST_PCIE_BRIDGE)] = { MM_PCIE_ATTRIB },
+    [PM_RESET_IDX(PM_RST_PCIE_CTRL)] = { MM_PCIE_ATTRIB },
+
+    [PM_RESET_IDX(PM_RST_DP)] = { MM_DP },
+    [PM_RESET_IDX(PM_RST_SWDT_CRF)] = { MM_SWDT },
+    [PM_RESET_IDX(PM_RST_AFI_FM5)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_AFI_FM4)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_AFI_FM3)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_AFI_FM2)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_AFI_FM1)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_AFI_FM0)] = { .hwdom_access = true },
 
     /* Channel 0 grants PM access.  */
-    [PM_RESET_IDX(PM_RESET_GDMA)] = { MM_GDMA_CH0 },
-    [PM_RESET_IDX(PM_RESET_GPU_PP1)] = { MM_GPU },
-    [PM_RESET_IDX(PM_RESET_GPU_PP0)] = { MM_GPU },
-    [PM_RESET_IDX(PM_RESET_GT)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_SATA)] = { MM_SATA_AHCI_HBA },
+    [PM_RESET_IDX(PM_RST_GDMA)] = { MM_GDMA_CH0 },
+    [PM_RESET_IDX(PM_RST_GPU_PP1)] = { MM_GPU },
+    [PM_RESET_IDX(PM_RST_GPU_PP0)] = { MM_GPU },
+    [PM_RESET_IDX(PM_RST_GT)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_SATA)] = { MM_SATA_AHCI_HBA },
 
     /* We don't allow anyone to turn on/off the ACPUs.  */
-    [PM_RESET_IDX(PM_RESET_ACPU3_PWRON)] = { 0 },
-    [PM_RESET_IDX(PM_RESET_ACPU2_PWRON)] = { 0 },
-    [PM_RESET_IDX(PM_RESET_ACPU1_PWRON)] = { 0 },
-    [PM_RESET_IDX(PM_RESET_ACPU0_PWRON)] = { 0 },
-    [PM_RESET_IDX(PM_RESET_APU_L2)] = { 0 },
-    [PM_RESET_IDX(PM_RESET_ACPU3)] = { 0 },
-    [PM_RESET_IDX(PM_RESET_ACPU2)] = { 0 },
-    [PM_RESET_IDX(PM_RESET_ACPU1)] = { 0 },
-    [PM_RESET_IDX(PM_RESET_ACPU0)] = { 0 },
-
-    [PM_RESET_IDX(PM_RESET_DDR)] = { 0 },
-
-    [PM_RESET_IDX(PM_RESET_APM_FPD)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_SOFT)] = { .hwdom_access = true },
-
-    [PM_RESET_IDX(PM_RESET_GEM0)] = { MM_GEM0 },
-    [PM_RESET_IDX(PM_RESET_GEM1)] = { MM_GEM1 },
-    [PM_RESET_IDX(PM_RESET_GEM2)] = { MM_GEM2 },
-    [PM_RESET_IDX(PM_RESET_GEM3)] = { MM_GEM3 },
-
-    [PM_RESET_IDX(PM_RESET_QSPI)] = { MM_QSPI },
-    [PM_RESET_IDX(PM_RESET_UART0)] = { MM_UART0 },
-    [PM_RESET_IDX(PM_RESET_UART1)] = { MM_UART1 },
-    [PM_RESET_IDX(PM_RESET_SPI0)] = { MM_SPI0 },
-    [PM_RESET_IDX(PM_RESET_SPI1)] = { MM_SPI1 },
-    [PM_RESET_IDX(PM_RESET_SDIO0)] = { MM_SD0 },
-    [PM_RESET_IDX(PM_RESET_SDIO1)] = { MM_SD1 },
-    [PM_RESET_IDX(PM_RESET_CAN0)] = { MM_CAN0 },
-    [PM_RESET_IDX(PM_RESET_CAN1)] = { MM_CAN1 },
-    [PM_RESET_IDX(PM_RESET_I2C0)] = { MM_I2C0 },
-    [PM_RESET_IDX(PM_RESET_I2C1)] = { MM_I2C1 },
-    [PM_RESET_IDX(PM_RESET_TTC0)] = { MM_TTC0 },
-    [PM_RESET_IDX(PM_RESET_TTC1)] = { MM_TTC1 },
-    [PM_RESET_IDX(PM_RESET_TTC2)] = { MM_TTC2 },
-    [PM_RESET_IDX(PM_RESET_TTC3)] = { MM_TTC3 },
-    [PM_RESET_IDX(PM_RESET_SWDT_CRL)] = { MM_SWDT },
-    [PM_RESET_IDX(PM_RESET_NAND)] = { MM_NAND },
+    [PM_RESET_IDX(PM_RST_ACPU3_PWRON)] = { 0 },
+    [PM_RESET_IDX(PM_RST_ACPU2_PWRON)] = { 0 },
+    [PM_RESET_IDX(PM_RST_ACPU1_PWRON)] = { 0 },
+    [PM_RESET_IDX(PM_RST_ACPU0_PWRON)] = { 0 },
+    [PM_RESET_IDX(PM_RST_APU_L2)] = { 0 },
+    [PM_RESET_IDX(PM_RST_ACPU3)] = { 0 },
+    [PM_RESET_IDX(PM_RST_ACPU2)] = { 0 },
+    [PM_RESET_IDX(PM_RST_ACPU1)] = { 0 },
+    [PM_RESET_IDX(PM_RST_ACPU0)] = { 0 },
+
+    [PM_RESET_IDX(PM_RST_DDR)] = { 0 },
+
+    [PM_RESET_IDX(PM_RST_APM_FPD)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_SOFT)] = { .hwdom_access = true },
+
+    [PM_RESET_IDX(PM_RST_GEM0)] = { MM_GEM0 },
+    [PM_RESET_IDX(PM_RST_GEM1)] = { MM_GEM1 },
+    [PM_RESET_IDX(PM_RST_GEM2)] = { MM_GEM2 },
+    [PM_RESET_IDX(PM_RST_GEM3)] = { MM_GEM3 },
+
+    [PM_RESET_IDX(PM_RST_QSPI)] = { MM_QSPI },
+    [PM_RESET_IDX(PM_RST_UART0)] = { MM_UART0 },
+    [PM_RESET_IDX(PM_RST_UART1)] = { MM_UART1 },
+    [PM_RESET_IDX(PM_RST_SPI0)] = { MM_SPI0 },
+    [PM_RESET_IDX(PM_RST_SPI1)] = { MM_SPI1 },
+    [PM_RESET_IDX(PM_RST_SDIO0)] = { MM_SD0 },
+    [PM_RESET_IDX(PM_RST_SDIO1)] = { MM_SD1 },
+    [PM_RESET_IDX(PM_RST_CAN0)] = { MM_CAN0 },
+    [PM_RESET_IDX(PM_RST_CAN1)] = { MM_CAN1 },
+    [PM_RESET_IDX(PM_RST_I2C0)] = { MM_I2C0 },
+    [PM_RESET_IDX(PM_RST_I2C1)] = { MM_I2C1 },
+    [PM_RESET_IDX(PM_RST_TTC0)] = { MM_TTC0 },
+    [PM_RESET_IDX(PM_RST_TTC1)] = { MM_TTC1 },
+    [PM_RESET_IDX(PM_RST_TTC2)] = { MM_TTC2 },
+    [PM_RESET_IDX(PM_RST_TTC3)] = { MM_TTC3 },
+    [PM_RESET_IDX(PM_RST_SWDT_CRL)] = { MM_SWDT },
+    [PM_RESET_IDX(PM_RST_NAND)] = { MM_NAND },
     /* ADMA Channel 0 grants access to pull the reset signal.  */
-    [PM_RESET_IDX(PM_RESET_ADMA)] = { MM_ADMA_CH0 },
-    [PM_RESET_IDX(PM_RESET_GPIO)] = { MM_GPIO },
+    [PM_RESET_IDX(PM_RST_ADMA)] = { MM_ADMA_CH0 },
+    [PM_RESET_IDX(PM_RST_GPIO)] = { MM_GPIO },
     /* FIXME: What is this?  */
-    [PM_RESET_IDX(PM_RESET_IOU_CC)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_TIMESTAMP)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_RPU_R50)] = { MM_RPU },
-    [PM_RESET_IDX(PM_RESET_RPU_R51)] = { MM_RPU },
-    [PM_RESET_IDX(PM_RESET_RPU_AMBA)] = { MM_RPU },
-    [PM_RESET_IDX(PM_RESET_OCM)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_RPU_PGE)] = { MM_RPU },
-
-    [PM_RESET_IDX(PM_RESET_USB0_CORERESET)] = { MM_USB3_0_XHCI },
-    [PM_RESET_IDX(PM_RESET_USB0_HIBERRESET)] = { MM_USB3_0_XHCI },
-    [PM_RESET_IDX(PM_RESET_USB0_APB)] = { MM_USB3_0_XHCI },
-
-    [PM_RESET_IDX(PM_RESET_USB1_CORERESET)] = { MM_USB3_1_XHCI },
-    [PM_RESET_IDX(PM_RESET_USB1_HIBERRESET)] = { MM_USB3_1_XHCI },
-    [PM_RESET_IDX(PM_RESET_USB1_APB)] = { MM_USB3_1_XHCI },
-
-    [PM_RESET_IDX(PM_RESET_IPI)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_APM_LPD)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_RTC)] = { MM_RTC },
-    [PM_RESET_IDX(PM_RESET_SYSMON)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_AFI_FM6)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_LPD_SWDT)] = { MM_SWDT },
-    [PM_RESET_IDX(PM_RESET_FPD)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_RPU_DBG1)] = { MM_RPU },
-    [PM_RESET_IDX(PM_RESET_RPU_DBG0)] = { MM_RPU },
-    [PM_RESET_IDX(PM_RESET_DBG_LPD)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_DBG_FPD)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_0)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_1)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_2)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_3)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_4)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_5)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_6)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_7)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_8)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_9)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_10)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_11)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_12)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_13)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_14)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_15)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_16)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_17)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_18)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_19)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_20)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_21)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_22)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_23)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_24)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_25)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_26)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_27)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_28)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_29)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_30)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_GPO3_PL_31)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_RPU_LS)] = { MM_RPU },
-    [PM_RESET_IDX(PM_RESET_PS_ONLY)] = { .hwdom_access = true },
-    [PM_RESET_IDX(PM_RESET_PL)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_IOU_CC)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_TIMESTAMP)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_RPU_R50)] = { MM_RPU },
+    [PM_RESET_IDX(PM_RST_RPU_R51)] = { MM_RPU },
+    [PM_RESET_IDX(PM_RST_RPU_AMBA)] = { MM_RPU },
+    [PM_RESET_IDX(PM_RST_OCM)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_RPU_PGE)] = { MM_RPU },
+
+    [PM_RESET_IDX(PM_RST_USB0_CORERESET)] = { MM_USB3_0_XHCI },
+    [PM_RESET_IDX(PM_RST_USB0_HIBERRESET)] = { MM_USB3_0_XHCI },
+    [PM_RESET_IDX(PM_RST_USB0_APB)] = { MM_USB3_0_XHCI },
+
+    [PM_RESET_IDX(PM_RST_USB1_CORERESET)] = { MM_USB3_1_XHCI },
+    [PM_RESET_IDX(PM_RST_USB1_HIBERRESET)] = { MM_USB3_1_XHCI },
+    [PM_RESET_IDX(PM_RST_USB1_APB)] = { MM_USB3_1_XHCI },
+
+    [PM_RESET_IDX(PM_RST_IPI)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_APM_LPD)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_RTC)] = { MM_RTC },
+    [PM_RESET_IDX(PM_RST_SYSMON)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_AFI_FM6)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_LPD_SWDT)] = { MM_SWDT },
+    [PM_RESET_IDX(PM_RST_FPD)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_RPU_DBG1)] = { MM_RPU },
+    [PM_RESET_IDX(PM_RST_RPU_DBG0)] = { MM_RPU },
+    [PM_RESET_IDX(PM_RST_DBG_LPD)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_DBG_FPD)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_0)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_1)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_2)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_3)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_4)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_5)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_6)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_7)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_8)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_9)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_10)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_11)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_12)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_13)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_14)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_15)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_16)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_17)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_18)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_19)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_20)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_21)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_22)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_23)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_24)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_25)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_26)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_27)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_28)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_29)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_30)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_GPO3_PL_31)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_RPU_LS)] = { MM_RPU },
+    [PM_RESET_IDX(PM_RST_PS_ONLY)] = { .hwdom_access = true },
+    [PM_RESET_IDX(PM_RST_PL)] = { .hwdom_access = true },
 };
 
 /*

diff --git a/xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h b/xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h
index e9a6ebfd4aaf78e892d5d608eb8c3f6313a8b250..b19c4a9d470107e6c05f1cd104e0926d437f36b6 100644 (file)
--- a/xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h
+++ b/xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h
@@ -208,124 +208,124 @@ enum pm_node_id {
 };
 
 enum pm_reset {
-       PM_RESET_START = 999,
-       PM_RESET_PCIE_CFG,
-       PM_RESET_PCIE_BRIDGE,
-       PM_RESET_PCIE_CTRL,
-       PM_RESET_DP,
-       PM_RESET_SWDT_CRF,
-       PM_RESET_AFI_FM5,
-       PM_RESET_AFI_FM4,
-       PM_RESET_AFI_FM3,
-       PM_RESET_AFI_FM2,
-       PM_RESET_AFI_FM1,
-       PM_RESET_AFI_FM0,
-       PM_RESET_GDMA,
-       PM_RESET_GPU_PP1,
-       PM_RESET_GPU_PP0,
-       PM_RESET_GPU,
-       PM_RESET_GT,
-       PM_RESET_SATA,
-       PM_RESET_ACPU3_PWRON,
-       PM_RESET_ACPU2_PWRON,
-       PM_RESET_ACPU1_PWRON,
-       PM_RESET_ACPU0_PWRON,
-       PM_RESET_APU_L2,
-       PM_RESET_ACPU3,
-       PM_RESET_ACPU2,
-       PM_RESET_ACPU1,
-       PM_RESET_ACPU0,
-       PM_RESET_DDR,
-       PM_RESET_APM_FPD,
-       PM_RESET_SOFT,
-       PM_RESET_GEM0,
-       PM_RESET_GEM1,
-       PM_RESET_GEM2,
-       PM_RESET_GEM3,
-       PM_RESET_QSPI,
-       PM_RESET_UART0,
-       PM_RESET_UART1,
-       PM_RESET_SPI0,
-       PM_RESET_SPI1,
-       PM_RESET_SDIO0,
-       PM_RESET_SDIO1,
-       PM_RESET_CAN0,
-       PM_RESET_CAN1,
-       PM_RESET_I2C0,
-       PM_RESET_I2C1,
-       PM_RESET_TTC0,
-       PM_RESET_TTC1,
-       PM_RESET_TTC2,
-       PM_RESET_TTC3,
-       PM_RESET_SWDT_CRL,
-       PM_RESET_NAND,
-       PM_RESET_ADMA,
-       PM_RESET_GPIO,
-       PM_RESET_IOU_CC,
-       PM_RESET_TIMESTAMP,
-       PM_RESET_RPU_R50,
-       PM_RESET_RPU_R51,
-       PM_RESET_RPU_AMBA,
-       PM_RESET_OCM,
-       PM_RESET_RPU_PGE,
-       PM_RESET_USB0_CORERESET,
-       PM_RESET_USB1_CORERESET,
-       PM_RESET_USB0_HIBERRESET,
-       PM_RESET_USB1_HIBERRESET,
-       PM_RESET_USB0_APB,
-       PM_RESET_USB1_APB,
-       PM_RESET_IPI,
-       PM_RESET_APM_LPD,
-       PM_RESET_RTC,
-       PM_RESET_SYSMON,
-       PM_RESET_AFI_FM6,
-       PM_RESET_LPD_SWDT,
-       PM_RESET_FPD,
-       PM_RESET_RPU_DBG1,
-       PM_RESET_RPU_DBG0,
-       PM_RESET_DBG_LPD,
-       PM_RESET_DBG_FPD,
-       PM_RESET_APLL,
-       PM_RESET_DPLL,
-       PM_RESET_VPLL,
-       PM_RESET_IOPLL,
-       PM_RESET_RPLL,
-       PM_RESET_GPO3_PL_0,
-       PM_RESET_GPO3_PL_1,
-       PM_RESET_GPO3_PL_2,
-       PM_RESET_GPO3_PL_3,
-       PM_RESET_GPO3_PL_4,
-       PM_RESET_GPO3_PL_5,
-       PM_RESET_GPO3_PL_6,
-       PM_RESET_GPO3_PL_7,
-       PM_RESET_GPO3_PL_8,
-       PM_RESET_GPO3_PL_9,
-       PM_RESET_GPO3_PL_10,
-       PM_RESET_GPO3_PL_11,
-       PM_RESET_GPO3_PL_12,
-       PM_RESET_GPO3_PL_13,
-       PM_RESET_GPO3_PL_14,
-       PM_RESET_GPO3_PL_15,
-       PM_RESET_GPO3_PL_16,
-       PM_RESET_GPO3_PL_17,
-       PM_RESET_GPO3_PL_18,
-       PM_RESET_GPO3_PL_19,
-       PM_RESET_GPO3_PL_20,
-       PM_RESET_GPO3_PL_21,
-       PM_RESET_GPO3_PL_22,
-       PM_RESET_GPO3_PL_23,
-       PM_RESET_GPO3_PL_24,
-       PM_RESET_GPO3_PL_25,
-       PM_RESET_GPO3_PL_26,
-       PM_RESET_GPO3_PL_27,
-       PM_RESET_GPO3_PL_28,
-       PM_RESET_GPO3_PL_29,
-       PM_RESET_GPO3_PL_30,
-       PM_RESET_GPO3_PL_31,
-       PM_RESET_RPU_LS,
-       PM_RESET_PS_ONLY,
-       PM_RESET_PL,
-       PM_RESET_END
+       PM_RST_START = 999,
+       PM_RST_PCIE_CFG,
+       PM_RST_PCIE_BRIDGE,
+       PM_RST_PCIE_CTRL,
+       PM_RST_DP,
+       PM_RST_SWDT_CRF,
+       PM_RST_AFI_FM5,
+       PM_RST_AFI_FM4,
+       PM_RST_AFI_FM3,
+       PM_RST_AFI_FM2,
+       PM_RST_AFI_FM1,
+       PM_RST_AFI_FM0,
+       PM_RST_GDMA,
+       PM_RST_GPU_PP1,
+       PM_RST_GPU_PP0,
+       PM_RST_GPU,
+       PM_RST_GT,
+       PM_RST_SATA,
+       PM_RST_ACPU3_PWRON,
+       PM_RST_ACPU2_PWRON,
+       PM_RST_ACPU1_PWRON,
+       PM_RST_ACPU0_PWRON,
+       PM_RST_APU_L2,
+       PM_RST_ACPU3,
+       PM_RST_ACPU2,
+       PM_RST_ACPU1,
+       PM_RST_ACPU0,
+       PM_RST_DDR,
+       PM_RST_APM_FPD,
+       PM_RST_SOFT,
+       PM_RST_GEM0,
+       PM_RST_GEM1,
+       PM_RST_GEM2,
+       PM_RST_GEM3,
+       PM_RST_QSPI,
+       PM_RST_UART0,
+       PM_RST_UART1,
+       PM_RST_SPI0,
+       PM_RST_SPI1,
+       PM_RST_SDIO0,
+       PM_RST_SDIO1,
+       PM_RST_CAN0,
+       PM_RST_CAN1,
+       PM_RST_I2C0,
+       PM_RST_I2C1,
+       PM_RST_TTC0,
+       PM_RST_TTC1,
+       PM_RST_TTC2,
+       PM_RST_TTC3,
+       PM_RST_SWDT_CRL,
+       PM_RST_NAND,
+       PM_RST_ADMA,
+       PM_RST_GPIO,
+       PM_RST_IOU_CC,
+       PM_RST_TIMESTAMP,
+       PM_RST_RPU_R50,
+       PM_RST_RPU_R51,
+       PM_RST_RPU_AMBA,
+       PM_RST_OCM,
+       PM_RST_RPU_PGE,
+       PM_RST_USB0_CORERESET,
+       PM_RST_USB1_CORERESET,
+       PM_RST_USB0_HIBERRESET,
+       PM_RST_USB1_HIBERRESET,
+       PM_RST_USB0_APB,
+       PM_RST_USB1_APB,
+       PM_RST_IPI,
+       PM_RST_APM_LPD,
+       PM_RST_RTC,
+       PM_RST_SYSMON,
+       PM_RST_AFI_FM6,
+       PM_RST_LPD_SWDT,
+       PM_RST_FPD,
+       PM_RST_RPU_DBG1,
+       PM_RST_RPU_DBG0,
+       PM_RST_DBG_LPD,
+       PM_RST_DBG_FPD,
+       PM_RST_APLL,
+       PM_RST_DPLL,
+       PM_RST_VPLL,
+       PM_RST_IOPLL,
+       PM_RST_RPLL,
+       PM_RST_GPO3_PL_0,
+       PM_RST_GPO3_PL_1,
+       PM_RST_GPO3_PL_2,
+       PM_RST_GPO3_PL_3,
+       PM_RST_GPO3_PL_4,
+       PM_RST_GPO3_PL_5,
+       PM_RST_GPO3_PL_6,
+       PM_RST_GPO3_PL_7,
+       PM_RST_GPO3_PL_8,
+       PM_RST_GPO3_PL_9,
+       PM_RST_GPO3_PL_10,
+       PM_RST_GPO3_PL_11,
+       PM_RST_GPO3_PL_12,
+       PM_RST_GPO3_PL_13,
+       PM_RST_GPO3_PL_14,
+       PM_RST_GPO3_PL_15,
+       PM_RST_GPO3_PL_16,
+       PM_RST_GPO3_PL_17,
+       PM_RST_GPO3_PL_18,
+       PM_RST_GPO3_PL_19,
+       PM_RST_GPO3_PL_20,
+       PM_RST_GPO3_PL_21,
+       PM_RST_GPO3_PL_22,
+       PM_RST_GPO3_PL_23,
+       PM_RST_GPO3_PL_24,
+       PM_RST_GPO3_PL_25,
+       PM_RST_GPO3_PL_26,
+       PM_RST_GPO3_PL_27,
+       PM_RST_GPO3_PL_28,
+       PM_RST_GPO3_PL_29,
+       PM_RST_GPO3_PL_30,
+       PM_RST_GPO3_PL_31,
+       PM_RST_RPU_LS,
+       PM_RST_PS_ONLY,
+       PM_RST_PL,
+       PM_RST_END
 };
 
 enum pm_clock {