x86: rename XMM* features to SSE*

The latter are their canonical names, used already in the instruction
emulator.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 9d364d49c1f7894645a44d08c5431318d3290341..d65baa7bc050f1c791809e8991ae8faa1d8cf932 100644 (file)
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -205,12 +205,12 @@ static void __init early_cpu_detect(void)
                c->x86_model += ((eax >> 16) & 0xF) << 4;
        c->x86_mask = eax & 15;
        edx &= ~cleared_caps[cpufeat_word(X86_FEATURE_FPU)];
-       ecx &= ~cleared_caps[cpufeat_word(X86_FEATURE_XMM3)];
+       ecx &= ~cleared_caps[cpufeat_word(X86_FEATURE_SSE3)];
        if (edx & cpufeat_mask(X86_FEATURE_CLFLUSH))
                c->x86_cache_alignment = ((ebx >> 8) & 0xff) * 8;
        /* Leaf 0x1 capabilities filled in early for Xen. */
        c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx;
-       c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] = ecx;
+       c->x86_capability[cpufeat_word(X86_FEATURE_SSE3)] = ecx;
 
        if ( cpuid_eax(0x80000000) >= 0x80000008 )
                paddr_bits = cpuid_eax(0x80000008) & 0xff;
@@ -249,7 +249,7 @@ static void generic_identify(struct cpuinfo_x86 *c)
        c->cpuid_level = cpuid_eax(0);
        cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
        c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx;
-       c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] = ecx;
+       c->x86_capability[cpufeat_word(X86_FEATURE_SSE3)] = ecx;
 
        if ( cpu_has(c, X86_FEATURE_CLFLUSH) )
                c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 5bc2812e5ffd4333a4dcb521d3f2c6e9694a9763..255a1d669518b7657bfd39a2f7d3dd6c4e717536 100644 (file)
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -2029,7 +2029,7 @@ unsigned long hvm_cr4_guest_reserved_bits(const struct vcpu *v,bool_t restore)
              X86_CR4_PCE |
              (leaf1_edx & cpufeat_mask(X86_FEATURE_FXSR) ?
               X86_CR4_OSFXSR : 0) |
-             (leaf1_edx & cpufeat_mask(X86_FEATURE_XMM) ?
+             (leaf1_edx & cpufeat_mask(X86_FEATURE_SSE) ?
               X86_CR4_OSXMMEXCPT : 0) |
              ((restore || nestedhvm_enabled(v->domain)) &&
               (leaf1_ecx & cpufeat_mask(X86_FEATURE_VMXE)) ?

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index ac4cda32dc480c1dc78edfadb37356682dbe21e8..1238d017cb75ecac38e72dbfc64507fa358bcd47 100644 (file)
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -1963,7 +1963,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
             data |= X86_CR4_PGE;
         if ( edx & cpufeat_mask(X86_FEATURE_FXSR) )
             data |= X86_CR4_OSFXSR;
-        if ( edx & cpufeat_mask(X86_FEATURE_XMM) )
+        if ( edx & cpufeat_mask(X86_FEATURE_SSE) )
             data |= X86_CR4_OSXMMEXCPT;
         if ( ecx & cpufeat_mask(X86_FEATURE_VMXE) )
             data |= X86_CR4_VMXE;

diff --git a/xen/include/asm-x86/amd.h b/xen/include/asm-x86/amd.h
index 984d482eb6f818d7766f54079b8e9b779d5c2af8..9b74c49617d033375e12414075e6de82ed11bc72 100644 (file)
--- a/xen/include/asm-x86/amd.h
+++ b/xen/include/asm-x86/amd.h
@@ -22,7 +22,7 @@
        cpufeat_mask(X86_FEATURE_CMOV)  | cpufeat_mask(X86_FEATURE_PAT)    | \
        cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLUSH)| \
        cpufeat_mask(X86_FEATURE_MMX)   | cpufeat_mask(X86_FEATURE_FXSR)   | \
-       cpufeat_mask(X86_FEATURE_XMM)   | cpufeat_mask(X86_FEATURE_XMM2))
+       cpufeat_mask(X86_FEATURE_SSE)   | cpufeat_mask(X86_FEATURE_SSE2))
 #define AMD_EXTFEATURES_K8_REV_C_ECX  0
 #define AMD_EXTFEATURES_K8_REV_C_EDX  (                                               \
        cpufeat_mask(X86_FEATURE_FPU)      | cpufeat_mask(X86_FEATURE_VME)   | \
@@ -48,7 +48,7 @@
 
 /* Family 0Fh, Revision E */
 #define AMD_FEATURES_K8_REV_E_ECX        (AMD_FEATURES_K8_REV_D_ECX |  \
-       cpufeat_mask(X86_FEATURE_XMM3))
+       cpufeat_mask(X86_FEATURE_SSE3))
 #define AMD_FEATURES_K8_REV_E_EDX        (AMD_FEATURES_K8_REV_D_EDX |  \
        cpufeat_mask(X86_FEATURE_HT))
 #define AMD_EXTFEATURES_K8_REV_E_ECX     (AMD_EXTFEATURES_K8_REV_D_ECX |\

diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 07ba368597cdb9e029a51d31b4d218a9a686e1d5..021427cd1f77c61eabecc9f48f933e99fd764740 100644 (file)
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -38,8 +38,8 @@
 #define X86_FEATURE_MMX                (0*32+23) /* Multimedia Extensions */
 #define X86_FEATURE_FXSR       (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
                                          /* of FPU context), and CR4.OSFXSR available */
-#define X86_FEATURE_XMM                (0*32+25) /* Streaming SIMD Extensions */
-#define X86_FEATURE_XMM2       (0*32+26) /* Streaming SIMD Extensions-2 */
+#define X86_FEATURE_SSE                (0*32+25) /* Streaming SIMD Extensions */
+#define X86_FEATURE_SSE2       (0*32+26) /* Streaming SIMD Extensions-2 */
 #define X86_FEATURE_SELFSNOOP  (0*32+27) /* CPU self snoop */
 #define X86_FEATURE_HT         (0*32+28) /* Hyper-Threading */
 #define X86_FEATURE_ACC                (0*32+29) /* Automatic clock control */
@@ -78,7 +78,7 @@
 #define X86_FEATURE_APERFMPERF   (3*32+16) /* APERFMPERF */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
-#define X86_FEATURE_XMM3       (4*32+ 0) /* Streaming SIMD Extensions-3 */
+#define X86_FEATURE_SSE3       (4*32+ 0) /* Streaming SIMD Extensions-3 */
 #define X86_FEATURE_PCLMULQDQ  (4*32+ 1) /* Carry-less mulitplication */
 #define X86_FEATURE_DTES64     (4*32+ 2) /* 64-bit Debug Store */
 #define X86_FEATURE_MWAIT      (4*32+ 3) /* Monitor/Mwait support */
@@ -183,7 +183,9 @@
 #define cpu_has_sep            boot_cpu_has(X86_FEATURE_SEP)
 #define cpu_has_mtrr           1
 #define cpu_has_mmx            1
-#define cpu_has_xmm3           boot_cpu_has(X86_FEATURE_XMM3)
+#define cpu_has_sse            boot_cpu_has(X86_FEATURE_SSE)
+#define cpu_has_sse2           boot_cpu_has(X86_FEATURE_SSE2)
+#define cpu_has_sse3           boot_cpu_has(X86_FEATURE_SSE3)
 #define cpu_has_ht             boot_cpu_has(X86_FEATURE_HT)
 #define cpu_has_mp             1
 #define cpu_has_nx             boot_cpu_has(X86_FEATURE_NX)