xen: arm: handle 32-bit guest CP register traps on 64-bit hypervisor

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Tim Deegan <tim@xen.org>

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 6be70fa0fe79a2acdf29bf3752097dd992ab0ea0..d1cf0e6ce4e3061318ca9b68a0195810d711e8e9 100644 (file)
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -700,16 +700,16 @@ static void do_cp15_32(struct cpu_user_regs *regs,
                     "attempt to write to read-only register CLIDR\n");
             domain_crash_synchronous();
         }
-        *r = READ_CP32(CLIDR);
+        *r = READ_SYSREG32(CLIDR_EL1);
         break;
     case HSR_CPREG32(CCSIDR):
         if ( !cp32.read )
         {
             dprintk(XENLOG_ERR,
-                    "attempt to write to read-only register CSSIDR\n");
+                    "attempt to write to read-only register CCSIDR\n");
             domain_crash_synchronous();
         }
-        *r = READ_CP32(CCSIDR);
+        *r = READ_SYSREG32(CCSIDR_EL1);
         break;
     case HSR_CPREG32(DCCISW):
         if ( cp32.read )
@@ -718,7 +718,11 @@ static void do_cp15_32(struct cpu_user_regs *regs,
                     "attempt to read from write-only register DCCISW\n");
             domain_crash_synchronous();
         }
+#ifdef CONFIG_ARM_32
         WRITE_CP32(*r, DCCISW);
+#else
+        asm volatile("dc cisw, %0;" : : "r" (*r) : "memory");
+#endif
         break;
     case HSR_CPREG32(CNTP_CTL):
     case HSR_CPREG32(CNTP_TVAL):