return trapnr < ARRAY_SIZE(strings) ? strings[trapnr] : "???";
}
+static const char *vec_name(unsigned int vec)
+{
+ static const char names[][4] = {
+#define P(x) [X86_EXC_ ## x] = "#" #x
+#define N(x) [X86_EXC_ ## x] = #x
+ P(DE), P(DB), N(NMI), P(BP), P(OF), P(BR), P(UD), P(NM),
+ P(DF), N(CSO), P(TS), P(NP), P(SS), P(GP), P(PF), N(SPV),
+ P(MF), P(AC), P(MC), P(XM), P(VE), P(CP),
+ P(HV), P(VC), P(SX),
+#undef N
+#undef P
+ };
+
+ return (vec < ARRAY_SIZE(names) && names[vec][0]) ? names[vec] : "???";
+}
+
/*
* This is called for faults at very unexpected times (e.g., when interrupts
* are disabled). In such situations we can't do much that is safe. We try to
}
}
- panic("FATAL TRAP: vector = %d (%s)\n"
- "[error_code=%04x] %s\n",
- trapnr, trapstr(trapnr), regs->error_code,
- (regs->eflags & X86_EFLAGS_IF) ? "" : ", IN INTERRUPT CONTEXT");
+ panic("FATAL TRAP: vec %u, %s[%04x]%s\n",
+ trapnr, vec_name(trapnr), regs->error_code,
+ (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
}
static void do_reserved_trap(struct cpu_user_regs *regs)
return;
show_execution_state(regs);
- panic("FATAL RESERVED TRAP %#x: %s\n", trapnr, trapstr(trapnr));
+ panic("FATAL RESERVED TRAP: vec %u, %s[%04x]\n",
+ trapnr, vec_name(trapnr), regs->error_code);
}
static void do_trap(struct cpu_user_regs *regs)
#define TRAP_virtualisation 20
#define TRAP_nr 32
-#define TRAP_HAVE_EC \
- ((1u << TRAP_double_fault) | (1u << TRAP_invalid_tss) | \
- (1u << TRAP_no_segment) | (1u << TRAP_stack_error) | \
- (1u << TRAP_gp_fault) | (1u << TRAP_page_fault) | \
- (1u << TRAP_alignment_check))
+#define TRAP_HAVE_EC X86_EXC_HAVE_EC
/* Set for entry via SYSCALL. Informs return code to use SYSRETQ not IRETQ. */
/* NB. Same as VGCF_in_syscall. No bits in common with any other TRAP_ defn. */
#define X86_NR_VECTORS 256
+/* Exception Vectors */
+#define X86_EXC_DE 0 /* Divide Error */
+#define X86_EXC_DB 1 /* Debug Exception */
+#define X86_EXC_NMI 2 /* NMI */
+#define X86_EXC_BP 3 /* Breakpoint */
+#define X86_EXC_OF 4 /* Overflow */
+#define X86_EXC_BR 5 /* BOUND Range */
+#define X86_EXC_UD 6 /* Invalid Opcode */
+#define X86_EXC_NM 7 /* Device Not Available */
+#define X86_EXC_DF 8 /* Double Fault */
+#define X86_EXC_CSO 9 /* Coprocessor Segment Overrun */
+#define X86_EXC_TS 10 /* Invalid TSS */
+#define X86_EXC_NP 11 /* Segment Not Present */
+#define X86_EXC_SS 12 /* Stack-Segment Fault */
+#define X86_EXC_GP 13 /* General Porection Fault */
+#define X86_EXC_PF 14 /* Page Fault */
+#define X86_EXC_SPV 15 /* PIC Spurious Interrupt Vector */
+#define X86_EXC_MF 16 /* Maths fault (x87 FPU) */
+#define X86_EXC_AC 17 /* Alignment Check */
+#define X86_EXC_MC 18 /* Machine Check */
+#define X86_EXC_XM 19 /* SIMD Exception */
+#define X86_EXC_VE 20 /* Virtualisation Exception */
+#define X86_EXC_CP 21 /* Control-flow Protection */
+#define X86_EXC_HV 28 /* Hypervisor Injection */
+#define X86_EXC_VC 29 /* VMM Communication */
+#define X86_EXC_SX 30 /* Security Exception */
+
+/* Bitmap of exceptions which have error codes. */
+#define X86_EXC_HAVE_EC \
+ ((1u << X86_EXC_DF) | (1u << X86_EXC_TS) | (1u << X86_EXC_NP) | \
+ (1u << X86_EXC_SS) | (1u << X86_EXC_GP) | (1u << X86_EXC_PF) | \
+ (1u << X86_EXC_AC) | (1u << X86_EXC_CP) | \
+ (1u << X86_EXC_VC) | (1u << X86_EXC_SX))
+
#endif /* __XEN_X86_DEFNS_H__ */