x86/mm: Move p2m type into bits of the PTE that the IOMMU doesn't use.

AMD IOMMU hardware uses bit 9 - bit 11 to encode lower page levels. p2m
type bits in p2m flags has to be shifted from bit 9 to bit 12.  Also,
bit 52 to bit 60 cannot be non-zero for iommu pde. So, the definition of
p2m_ram_rw has to be swapped with p2m_invalid.

Signed-off-by: Wei Wang <wei.wang2@amd.com>
Acked-by: Tim Deegan <Tim.Deegan@citrix.com>
Committed-by: Tim Deegan <Tim.Deegan@citrix.com>

diff --git a/xen/arch/x86/mm/p2m.c b/xen/arch/x86/mm/p2m.c
index 6bb61605c515ac8206ed42e36436efb194a32216..5ceb51cfd745b8487e5061e54dddde19a0da1279 100644 (file)
--- a/xen/arch/x86/mm/p2m.c
+++ b/xen/arch/x86/mm/p2m.c
@@ -80,7 +80,12 @@ unsigned long p2m_type_to_flags(p2m_type_t t, mfn_t mfn)
 {
     unsigned long flags;
 #ifdef __x86_64__
-    flags = (unsigned long)(t & 0x3fff) << 9;
+    /*
+     * AMD IOMMU: When we share p2m table with iommu, bit 9 - bit 11 will be
+     * used for iommu hardware to encode next io page level. Bit 59 - bit 62
+     * are used for iommu flags, We could not use these bits to store p2m types.
+     */
+    flags = (unsigned long)(t & 0x7f) << 12;
 #else
     flags = (t & 0x7UL) << 9;
 #endif
@@ -1826,6 +1831,9 @@ static mfn_t p2m_gfn_to_mfn_current(struct p2m_domain *p2m,
             p2mt = p2m_flags_to_type(l1e_get_flags(l1e));
             ASSERT(l1e_get_pfn(l1e) != INVALID_MFN || !p2m_is_ram(p2mt));
 
+            if ( l1e.l1 == 0 )
+                p2mt = p2m_invalid;
+
             if ( p2m_flags_to_type(l1e_get_flags(l1e))
                  == p2m_populate_on_demand )
             {

diff --git a/xen/include/asm-x86/p2m.h b/xen/include/asm-x86/p2m.h
index 0b35fb48e0e6db2cd5862a7aa77646b4ecf5c9cc..91b7ce69946c04b30df86c0df4b669518e03cca6 100644 (file)
--- a/xen/include/asm-x86/p2m.h
+++ b/xen/include/asm-x86/p2m.h
@@ -63,9 +63,15 @@
  * Further expansions of the type system will only be supported on
  * 64-bit Xen.
  */
+
+/*
+ * AMD IOMMU: When we share p2m table with iommu, bit 52 -bit 58 in pte 
+ * cannot be non-zero, otherwise, hardware generates io page faults when 
+ * device access those pages. Therefore, p2m_ram_rw has to be defined as 0.
+ */
 typedef enum {
-    p2m_invalid = 0,            /* Nothing mapped here */
-    p2m_ram_rw = 1,             /* Normal read/write guest RAM */
+    p2m_ram_rw = 0,             /* Normal read/write guest RAM */
+    p2m_invalid = 1,            /* Nothing mapped here */
     p2m_ram_logdirty = 2,       /* Temporarily read-only for log-dirty */
     p2m_ram_ro = 3,             /* Read-only; writes are silently dropped */
     p2m_mmio_dm = 4,            /* Reads and write go to the device model */
@@ -375,7 +381,13 @@ static inline p2m_type_t p2m_flags_to_type(unsigned long flags)
 {
     /* Type is stored in the "available" bits */
 #ifdef __x86_64__
-    return (flags >> 9) & 0x3fff;
+    /*
+     * AMD IOMMU: When we share p2m table with iommu, bit 9 - bit 11 will be
+     * used for iommu hardware to encode next io page level. Bit 59 - bit 62
+     * are used for iommu flags, We could not use these bits to store p2m types.
+     */
+
+    return (flags >> 12) & 0x7f;
 #else
     return (flags >> 9) & 0x7;
 #endif