x86/AMD: Enable WC+ memory type on family 10 processors

In some cases BIOS may not enable WC+ memory type on family 10 processors,
instead converting what would be WC+ memory to CD type. On guests using
nested pages this could result in performance degradation. This patch
enables WC+.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
Committed-by: Jan Beulich <jbeulich@suse.com>

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index b8d4a2abbaa19d23e0752fd1b50b189c950fca5a..27b7f71d8b527063d2bc8dab1972f15697b98c33 100644 (file)
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -485,6 +485,17 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
                        check_enable_amd_mmconf_dmi();
 
                fam10h_check_enable_mmcfg();
+
+               /*
+                * On family 10h BIOS may not have properly enabled WC+
+                * support, causing it to be converted to CD memtype. This may
+                * result in performance degradation for certain nested-paging
+                * guests. Prevent this conversion by clearing bit 24 in
+                * MSR_F10_BU_CFG2.
+                */
+               rdmsrl(MSR_F10_BU_CFG2, value);
+               value &= ~(1ULL << 24);
+               wrmsrl(MSR_F10_BU_CFG2, value);
        }
 
        /*

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 03f6f985b0c9380f4db36f433d6cfc214e401077..5c1de6e09696f5e8a263c9bd57ced73dfd8b901b 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -220,8 +220,9 @@
 #define MSR_F10_MC4_MISC2              0xc0000409
 #define MSR_F10_MC4_MISC3              0xc000040A
 
-/* AMD Family10h MMU control MSRs */
-#define MSR_F10_BU_CFG                  0xc0011023
+/* AMD Family10h Bus Unit MSRs */
+#define MSR_F10_BU_CFG                 0xc0011023
+#define MSR_F10_BU_CFG2                0xc001102a
 
 /* Other AMD Fam10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058