gsc3 = &gsc_3;
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#include <linux/of_irq.h>
#include <linux/io.h>
+#include <asm/mach/time.h>
#include <asm/cputype.h>
#include <asm/delay.h>
#include <asm/localtimer.h>
return -ENXIO;
if (arch_timer_rate == 0) {
+ arch_timer_reg_write(ARCH_TIMER_PHYS_ACCESS, ARCH_TIMER_REG_CTRL, 0);
freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS,
ARCH_TIMER_REG_FREQ);
setup_sched_clock(cnt32, 32, arch_timer_rate);
return 0;
}
+
+static void __init arch_timer_init(void)
+{
+ arch_timer_of_register();
+ arch_timer_sched_clock_init();
+}
+
+struct sys_timer arch_generic_timer = {
+ .init = arch_timer_init,
+};
select S5P_PM if PM
select S5P_SLEEP if PM
select SAMSUNG_DMADEV
+ select ARM_ARCH_TIMER
help
Enable EXYNOS5250 SoC support
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
extern struct sys_timer exynos4_timer;
+extern struct sys_timer arch_generic_timer;
struct map_desc;
void exynos_init_io(struct map_desc *mach_desc, int size);
.handle_irq = gic_handle_irq,
.init_machine = exynos5250_dt_machine_init,
.init_late = exynos_init_late,
- .timer = &exynos4_timer,
+ .timer = &arch_generic_timer,
.dt_compat = exynos5250_dt_compat,
.restart = exynos5_restart,
MACHINE_END