#define REG_DR_DSPASTRIDE 0x70188
#define REG_DR_PIPEACONF 0x70008
+#define REG_DR_DSPBSURF 0x7119C
+#define REG_DR_DSPBCNTR 0x71180
+#define REG_DR_DSPBSTRIDE 0x71188
+#define REG_DR_PIPEBCONF0x71008
+
extern int vga_passthrough;
uint32_t guest_framebuffer;
unsigned int *pipeaconf = (unsigned int *)(intel_mmio + REG_DR_PIPEACONF);
unsigned int *dspasurf = (unsigned int *)(intel_mmio + REG_DR_DSPASURF);
unsigned int *dspastride = (unsigned int *)(intel_mmio + REG_DR_DSPASTRIDE);
- unsigned int surf, pipea;
+
+ unsigned int *dspbcntr = (unsigned int *)(intel_mmio + REG_DR_DSPBCNTR);
+ unsigned int *pipebconf = (unsigned int *)(intel_mmio + REG_DR_PIPEBCONF);
+ unsigned int *dspbsurf = (unsigned int *)(intel_mmio + REG_DR_DSPBSURF);
+ unsigned int *dspbstride = (unsigned int *)(intel_mmio + REG_DR_DSPBSTRIDE);
+
+ unsigned int surfa, surfb, pipea, pipeb;
+ char pipebenabled = !!(*pipebconf & (1 << 30));
INTEL_DEBUG("DSPASURF CTRL: 0x%x\n", intel_get_reg(REG_DR_DSPACNTR));
*pipeaconf &= ~(0x3 << 18);
*dspacntr |= (1 << 31);
/* Address of the surface to map to */
- surf = *dspasurf;
+ surfa = *dspasurf;
*dspasurf = 0x00000000;
*dspacntr &= ~(1 << 31);
*dspasurf = 0x00000000;
*pipeaconf |= pipea;
+ if (pipebenabled) {
+ INTEL_DEBUG("PIPEBCONF enabled.\n");
+
+ /* Disable surface */
+ pipeb = *pipebconf & (0x3 << 18);
+ *pipebconf &= ~(0x3 << 18);
+ *dspbcntr |= (1 << 31);
+ /* Address of the surface to map to */
+ surfb = *dspbsurf;
+ *dspbsurf = 0x00000000;
+ *dspbcntr &= ~(1 << 31);
+ *dspbsurf = 0x00000000;
+ *pipebconf |= pipeb;
+ }
+
usleep(20000);
*pipeaconf &= ~(0x3 << 18);
/* Enable surface linear mode */
*dspacntr &= ~(1 << 10);
if (linesize) *dspastride = linesize;
- *dspasurf = surf;
+ *dspasurf = surfa;
*dspacntr |= (1 << 31);
*pipeaconf |= pipea;
+ if (pipebenabled) {
+ *pipebconf &= ~(0x3 << 18);
+ /* Enable surface linear mode */
+ *dspbcntr &= ~(1 << 10);
+ if (linesize) *dspbstride = linesize;
+ *dspbsurf = surfb;
+ *dspbcntr |= (1 << 31);
+ *pipebconf |= pipeb;
+ }
+
usleep(20000);
}