Preliminary MIPS64R2 mode.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3479 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 55c935e6d5eb7b425640a5a8a09f51ca991768d2..997858a69e0f5c363b65fbd1802952d370d48fd9 100644 (file)
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -276,6 +276,27 @@ static mips_def_t mips_defs[] =
         .SEGBITS = 40,
         .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
     },
+    {
+       /* A generic CPU providing MIPS64 Release 2 features.
+           FIXME: Eventually this should be replaced by a real CPU model. */
+        .name = "MIPS64R2-generic",
+        .CP0_PRid = 0x00000000,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (0x1 << CP0C0_AR),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+                   (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+                   (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+                   (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x36FBFFFF,
+        .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_L) |
+                    (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
+                    (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
+        .SEGBITS = 40,
+        .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
+    },
 #endif
 };