xen/arm: zynqmp: Add RPLL and VPLL-related clocks to pm_clock2node map

Current clock driver in Linux for Zynq MPSoC controls the PLLs as if they
are clocks (using the clock rather than PLL EEMI API). Only RPLL and VPLL
could be directly controlled by a guest that owns the display port, because
the display port driver in Linux requires for video and audio some special
clock frequencies, that further require VPLL and RPLL to be locked in fractional
modes (for video and audio respectively). Therefore, we need to allow a guest
that owns the display port to directly control these PLL-related clocks.

In future, Linux driver should switch to using PLL EEMI API for controlling
PLLs, and the support for that is already added in EEMI mediator in Xen.
Once that happens, this patch can be reverted.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Reviewed-by: Stefano Stabellini <stefanos@xilinx.com>

diff --git a/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c b/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c
index f5e643edabe20783ec848500c81767fec8fe68f1..69cbce4e97287f5cf074bfc1232829286551b793 100644 (file)
--- a/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c
+++ b/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c
@@ -433,6 +433,10 @@ static const struct pm_clock2node {
     enum pm_clock clock;
     enum pm_node_id node;
 } pm_clock_node_map[] = {
+    PM_CLOCK2NODE(PM_CLOCK_RPLL, NODE_DP),
+    PM_CLOCK2NODE(PM_CLOCK_VPLL, NODE_DP),
+    PM_CLOCK2NODE(PM_CLOCK_RPLL_TO_FPD, NODE_DP),
+    PM_CLOCK2NODE(PM_CLOCK_VPLL_TO_LPD, NODE_DP),
     PM_CLOCK2NODE(PM_CLOCK_DP_VIDEO_REF, NODE_DP),
     PM_CLOCK2NODE(PM_CLOCK_DP_AUDIO_REF, NODE_DP),
     PM_CLOCK2NODE(PM_CLOCK_DP_STC_REF, NODE_DP),
@@ -488,6 +492,14 @@ static const struct pm_clock2node {
     PM_CLOCK2NODE(PM_CLOCK_PL1_REF, NODE_PL),
     PM_CLOCK2NODE(PM_CLOCK_PL2_REF, NODE_PL),
     PM_CLOCK2NODE(PM_CLOCK_PL3_REF, NODE_PL),
+    PM_CLOCK2NODE(PM_CLOCK_RPLL_INT, NODE_DP),
+    PM_CLOCK2NODE(PM_CLOCK_RPLL_PRE_SRC, NODE_DP),
+    PM_CLOCK2NODE(PM_CLOCK_RPLL_INT_MUX, NODE_DP),
+    PM_CLOCK2NODE(PM_CLOCK_RPLL_POST_SRC, NODE_DP),
+    PM_CLOCK2NODE(PM_CLOCK_VPLL_INT, NODE_DP),
+    PM_CLOCK2NODE(PM_CLOCK_VPLL_PRE_SRC, NODE_DP),
+    PM_CLOCK2NODE(PM_CLOCK_VPLL_INT_MUX, NODE_DP),
+    PM_CLOCK2NODE(PM_CLOCK_VPLL_POST_SRC, NODE_DP),
     PM_CLOCK2NODE(PM_CLOCK_CAN0_MIO, NODE_CAN_0),
     PM_CLOCK2NODE(PM_CLOCK_CAN1_MIO, NODE_CAN_1),
     PM_CLOCK2NODE(PM_CLOCK_GEM0_REF, NODE_ETH_0),