]> xenbits.xensource.com Git - people/aperard/linux-arndale.git/commitdiff
USB3.0:dwc3:Enabling DT support for USB3.0 DWC3
authorYuvaraj CD <yuvaraj.cd@gmail.com>
Mon, 24 Dec 2012 11:36:49 +0000 (17:06 +0530)
committerVasanth Ananthan <vasanthananthan@gmail.com>
Tue, 8 Jan 2013 10:34:41 +0000 (16:04 +0530)
For internal use only.Made out of patches from Vivek Gautam
Signed-off-by: Yuvaraj C D <yuvaraj.cd@samsung.com>
arch/arm/boot/dts/exynos5250.dtsi
arch/arm/mach-exynos/Kconfig
arch/arm/mach-exynos/clock-exynos5.c
arch/arm/mach-exynos/include/mach/map.h
arch/arm/mach-exynos/include/mach/regs-pmu.h
arch/arm/mach-exynos/mach-exynos5-dt.c
arch/arm/plat-samsung/include/plat/devs.h
drivers/usb/Kconfig
drivers/usb/core/hub.c
drivers/usb/dwc3/dwc3-exynos.c
drivers/usb/host/xhci-plat.c

index 32a0d15f7017f343437fd6dc76581ed9f1d71c0c..ca27be6d65e784e5437889f84f90c97225f55923 100644 (file)
                interrupts = <0 71 0>;
        };
 
+
+       usb@12000000 {
+               compatible = "samsung,exynos-dwc3";
+               reg = <0x12000000 0x10000>;
+               interrupts = <0 72 0>;
+       };
+       
        rtc {
                compatible = "samsung,s3c6410-rtc";
                reg = <0x101E0000 0x100>;
index 7e0258ff05579588b13f955c74a12a05002cff98..adc4f511b913824cb562d62b5e0658751f41196e 100644 (file)
@@ -422,6 +422,7 @@ config MACH_EXYNOS5_DT
        select SOC_EXYNOS5250
        select USE_OF
        select EXYNOS4_SETUP_USB_PHY
+       select USB_ARCH_HAS_XHCI
        help
          Machine support for Samsung EXYNOS5 machine with device tree enabled.
          Select this if a fdt blob is available for the EXYNOS5 SoC based board.
index c44ca1ee1b8d0196de2ac413bad5af226bc83bc9..b00b6bf3f2ee6db8f50a17cb5e265c29051067f0 100644 (file)
@@ -719,6 +719,11 @@ static struct clk exynos5_init_clocks_off[] = {
                .name           = "usbhost",
                .enable         = exynos5_clk_ip_fsys_ctrl ,
                .ctrlbit        = (1 << 18),
+       }, {
+               .name           = "usbdrd30",
+               .parent         = &exynos5_clk_aclk_200.clk,
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 19),
        }, {
                .name           = "usbotg",
                .enable         = exynos5_clk_ip_fsys_ctrl,
@@ -984,6 +989,16 @@ struct clksrc_sources exynos5_clkset_group = {
        .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
 };
 
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+       [0] = &exynos5_clk_mout_mpll.clk,
+       [1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+       .sources        = exynos5_clkset_usbdrd30_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
 /* Possible clock sources for aclk_266_gscl_sub Mux */
 static struct clk *clk_src_gscl_266_list[] = {
        [0] = &clk_ext_xtal_mux,
@@ -1268,7 +1283,17 @@ static struct clksrc_clk exynos5_clksrcs[] = {
                        .parent         = &exynos5_clk_mout_cpll.clk,
                },
                .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
-       },
+       }, {
+
+               .clk    = {
+                       .name           = "sclk_usbdrd30",
+                       .enable         = exynos5_clksrc_mask_fsys_ctrl,
+                       .ctrlbit        = (1 << 28),
+               },
+               .sources = &exynos5_clkset_usbdrd30,
+               .reg_src = {.reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1},
+               .reg_div = {.reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4},
+       }
 };
 
 /* Clock initialization code */
index 0083aa4676103b40cb7bba7595b907be2d3247cf..d3190e6788eebe5d1a2e4d976484d5a313811125 100644 (file)
 #define EXYNOS4_PA_EHCI                        0x12580000
 #define EXYNOS4_PA_OHCI                        0x12590000
 #define EXYNOS4_PA_HSPHY               0x125B0000
+#define EXYNOS5_PA_DRD                 0x12000000
+#define EXYNOS5_PA_EHCI                        0x12110000
+#define EXYNOS5_PA_OHCI                        0x12120000
 #define EXYNOS4_PA_MFC                 0x13400000
 
 #define EXYNOS4_PA_UART                        0x13800000
 #define S3C_PA_SPI1                    EXYNOS4_PA_SPI1
 #define S3C_PA_SPI2                    EXYNOS4_PA_SPI2
 #define S3C_PA_USB_HSOTG               EXYNOS4_PA_HSOTG
-
+#define S3C_PA_USB_PHY                 EXYNOS4_PA_HSPHY
 #define S5P_PA_EHCI                    EXYNOS4_PA_EHCI
 #define S5P_PA_FIMC0                   EXYNOS4_PA_FIMC0
 #define S5P_PA_FIMC1                   EXYNOS4_PA_FIMC1
index d4e392b811a315d6a477f677b4462359ed9c8f6f..fc02178806be9c5eda818158348d4d7eaee27583 100644 (file)
 
 /* For EXYNOS5 */
 
-#define EXYNOS5_USB_CFG                                                S5P_PMUREG(0x0230)
 
 #define EXYNOS5_AUTO_WDTRESET_DISABLE                          S5P_PMUREG(0x0408)
 #define EXYNOS5_MASK_WDTRESET_REQUEST                          S5P_PMUREG(0x040C)
index 6f82cf96da08313d908bee1952d70b4ac8466818..82247fd3bcd63cbc4077828f277fae79fa1e1386 100644 (file)
@@ -114,6 +114,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                "exynos-ohci", &smdk5250_ohci_pdata),
        OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
                                "s5p-ehci", &smdk5250_ehci_pdata),
+       OF_DEV_AUXDATA("samsung,exynos-dwc3", EXYNOS5_PA_DRD,
+                               "exynos-dwc3", NULL),
        {},
 };
 
index 5da4b4f38f40ebb41c076fbe74bd205aefefdacf..001fdc1695e601ef1d229a750662ee787cf784b1 100644 (file)
@@ -138,7 +138,6 @@ extern struct platform_device exynos_device_drm;
 extern struct platform_device samsung_asoc_dma;
 extern struct platform_device samsung_asoc_idma;
 extern struct platform_device samsung_device_keypad;
-
 /* s3c2440 specific devices */
 
 #ifdef CONFIG_CPU_S3C2440
index 4c90b510d0160c246f1fd5c6c280a88d091c80f8..0454b8a8e0a9ae6ffa60d363a850369af66662e0 100644 (file)
@@ -53,6 +53,7 @@ config USB_ARCH_HAS_EHCI
 # some non-PCI HCDs implement xHCI
 config USB_ARCH_HAS_XHCI
        boolean
+       default y if ARCH_EXYNOS5
        default PCI
 
 menuconfig USB_SUPPORT
index 1af04bdeaf0c1884487ed830bcee7dd32ee720b6..17c7daf14f4441c288e42dff4aab5f3a1901475d 100644 (file)
@@ -1611,7 +1611,6 @@ static int hub_probe(struct usb_interface *intf, const struct usb_device_id *id)
 
        desc = intf->cur_altsetting;
        hdev = interface_to_usbdev(intf);
-
        /* Hubs have proper suspend/resume support. */
        usb_enable_autosuspend(hdev);
 
index ca6597853f90339358bf670e37e1cad2f65cf4cc..08998f7a5f91639aee172fa817f861ae282bbf86 100644 (file)
@@ -21,7 +21,7 @@
 #include <linux/clk.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/nop-usb-xceiv.h>
-
+#include <linux/of.h>
 #include "core.h"
 
 struct dwc3_exynos {
@@ -87,9 +87,10 @@ err1:
        return ret;
 }
 
+static u64 dwc3_exynos_dma_mask = DMA_BIT_MASK(32);
+
 static int __devinit dwc3_exynos_probe(struct platform_device *pdev)
 {
-       struct dwc3_exynos_data *pdata = pdev->dev.platform_data;
        struct platform_device  *dwc3;
        struct dwc3_exynos      *exynos;
        struct clk              *clk;
@@ -102,6 +103,13 @@ static int __devinit dwc3_exynos_probe(struct platform_device *pdev)
                dev_err(&pdev->dev, "not enough memory\n");
                goto err0;
        }
+       /*
+        * Right now device-tree probed devices don't get dma_mask set.
+        * Since shared usb code relies on it, set it here for now.
+        * Once we move to full device tree support this will vanish off.
+        */
+       if (!pdev->dev.dma_mask)
+               pdev->dev.dma_mask = &dwc3_exynos_dma_mask;
 
        platform_set_drvdata(pdev, exynos);
 
@@ -139,14 +147,6 @@ static int __devinit dwc3_exynos_probe(struct platform_device *pdev)
 
        clk_enable(exynos->clk);
 
-       /* PHY initialization */
-       if (!pdata) {
-               dev_dbg(&pdev->dev, "missing platform data\n");
-       } else {
-               if (pdata->phy_init)
-                       pdata->phy_init(pdev, pdata->phy_type);
-       }
-
        ret = platform_device_add_resources(dwc3, pdev->resource,
                        pdev->num_resources);
        if (ret) {
@@ -163,9 +163,6 @@ static int __devinit dwc3_exynos_probe(struct platform_device *pdev)
        return 0;
 
 err4:
-       if (pdata && pdata->phy_exit)
-               pdata->phy_exit(pdev, pdata->phy_type);
-
        clk_disable(clk);
        clk_put(clk);
 err3:
@@ -181,7 +178,6 @@ err0:
 static int __devexit dwc3_exynos_remove(struct platform_device *pdev)
 {
        struct dwc3_exynos      *exynos = platform_get_drvdata(pdev);
-       struct dwc3_exynos_data *pdata = pdev->dev.platform_data;
 
        platform_device_unregister(exynos->dwc3);
        platform_device_unregister(exynos->usb2_phy);
@@ -189,9 +185,6 @@ static int __devexit dwc3_exynos_remove(struct platform_device *pdev)
 
        dwc3_put_device_id(exynos->dwc3->id);
 
-       if (pdata && pdata->phy_exit)
-               pdata->phy_exit(pdev, pdata->phy_type);
-
        clk_disable(exynos->clk);
        clk_put(exynos->clk);
 
@@ -200,11 +193,20 @@ static int __devexit dwc3_exynos_remove(struct platform_device *pdev)
        return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id exynos_dwc3_match[] = {
+       { .compatible = "samsung,exynos-dwc3" },
+       {},
+};
+MODULE_DEVICE_TABLE(of, exynos_dwc3_match);
+#endif
+
 static struct platform_driver dwc3_exynos_driver = {
        .probe          = dwc3_exynos_probe,
        .remove         = __devexit_p(dwc3_exynos_remove),
        .driver         = {
                .name   = "exynos-dwc3",
+               .of_match_table = of_match_ptr(exynos_dwc3_match),
        },
 };
 
index df90fe51b4aa2d406b8b2f8bfa591c410df89a35..2d163d8215359bfc8eb0aade626486018475df43 100644 (file)
@@ -93,7 +93,6 @@ static int xhci_plat_probe(struct platform_device *pdev)
 
        if (usb_disabled())
                return -ENODEV;
-
        driver = &xhci_plat_xhci_driver;
 
        irq = platform_get_irq(pdev, 0);