c/s
62b187969 "x86: further CPUID handling adjustments" make some adjustments.
However, it breaks levelling of guests, making it impossible for the toolstack
to hide STIBP or IBPB from guests on hardware with up-to-date microcode.
The dom0 issue referenced in the commit message was fixed by the hunk
adjusting the zeroing alone. STIBP and IBPB don't need (and indeed, must not
be for levelling purposes) OR'd into the leaf.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
special_features[FEATURESET_7b0]);
*ecx &= hvm_featureset[FEATURESET_7c0];
-
- *edx |= cpufeat_mask(X86_FEATURE_STIBP);
*edx &= hvm_featureset[FEATURESET_7d0];
/* Don't expose HAP-only features to non-hap guests. */
hvm_cpuid(0x80000001, NULL, NULL, NULL, &_edx);
*eax |= (_edx & cpufeat_mask(X86_FEATURE_LM) ? vaddr_bits : 32) << 8;
- *ebx |= cpufeat_mask(X86_FEATURE_IBPB);
*ebx &= hvm_featureset[FEATURESET_e8b];
break;
}
special_features[FEATURESET_7b0]);
c &= pv_featureset[FEATURESET_7c0];
-
- d |= cpufeat_mask(X86_FEATURE_STIBP);
d &= pv_featureset[FEATURESET_7d0];
if ( !is_pvh_domain(currd) )
case 0x80000008:
a = paddr_bits | (vaddr_bits << 8);
- b |= cpufeat_mask(X86_FEATURE_IBPB);
b &= pv_featureset[FEATURESET_e8b];
break;