apic_phys = mp_lapic_addr;
set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
- apic_printk(APIC_VERBOSE, "mapped APIC to %08Lx (%08lx)\n", APIC_BASE,
- apic_phys);
+ apic_printk(APIC_VERBOSE, "mapped APIC to %p (%08lx)\n",
+ fix_to_virt(FIX_APIC_BASE), apic_phys);
__next:
/*
static inline void apic_mem_write(unsigned int reg, uint32_t v)
{
- *((volatile u32 *)(APIC_BASE+reg)) = v;
+ volatile uint32_t *addr = fix_to_virt(FIX_APIC_BASE) + reg;
+
+ *addr = v;
}
-static inline u32 apic_mem_read(unsigned int reg)
+static inline uint32_t apic_mem_read(unsigned int reg)
{
- return *((volatile u32 *)(APIC_BASE+reg));
+ const volatile uint32_t *addr = fix_to_virt(FIX_APIC_BASE) + reg;
+
+ return *addr;
}
/* NOTE: in x2APIC mode, we should use apic_icr_write()/apic_icr_read() to
/* Applicable to vectors, TPR, and PPR. */
#define APIC_PRIO_CLASS(v) ((v) & 0xF0)
-#define APIC_BASE __fix_to_virt(FIX_APIC_BASE)
-
#define MAX_IO_APICS 128
extern bool x2apic_enabled;
}
set_fixmap_nocache(idx, ioapic_phys);
- apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08Lx (%08lx)\n",
- __fix_to_virt(idx), ioapic_phys);
+ apic_printk(APIC_VERBOSE, "mapped IOAPIC to %p (%08lx)\n",
+ fix_to_virt(idx), ioapic_phys);
if ( bad_ioapic_register(i) )
{