platform: zynqmp: rename clock node macros

To maintain future compatibility, rename clock node macros to have
PM_CLK_* prefix instead of previously used PM_CLOCK_* prefix.

Signed-off-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@xilinx.com>
Signed-off-by: Stefano Stabellini <stefano.stabellini@xilinx.com>
Reviewed-by: Stefano Stabellini <stefano.stabellini@xilinx.com>

diff --git a/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c b/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c
index d1ef6462a48580ca6bb12851f3e7eedbf9cb814b..6f48497ca0510bd82390825769f540ecf9084afa 100644 (file)
--- a/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c
+++ b/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c
@@ -439,89 +439,89 @@ static const struct pm_clock2node {
     enum pm_clock clock;
     enum pm_node_id node;
 } pm_clock_node_map[] = {
-    PM_CLOCK2NODE(PM_CLOCK_RPLL, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_VPLL, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_RPLL_TO_FPD, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_VPLL_TO_LPD, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_DP_VIDEO_REF, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_DP_AUDIO_REF, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_DP_STC_REF, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_GDMA_REF, PM_DEV_GDMA),
-    PM_CLOCK2NODE(PM_CLOCK_DPDMA_REF, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_SATA_REF, PM_DEV_SATA),
-    PM_CLOCK2NODE(PM_CLOCK_PCIE_REF, PM_DEV_PCIE),
-    PM_CLOCK2NODE(PM_CLOCK_GPU_REF, PM_DEV_GPU),
-    PM_CLOCK2NODE(PM_CLOCK_GPU_PP0_REF, PM_DEV_GPU),
-    PM_CLOCK2NODE(PM_CLOCK_GPU_PP1_REF, PM_DEV_GPU),
-    PM_CLOCK2NODE(PM_CLOCK_TOPSW_LSBUS, PM_DEV_DDR),
-    PM_CLOCK2NODE(PM_CLOCK_LPD_LSBUS, PM_DEV_TTC_0),
-    PM_CLOCK2NODE(PM_CLOCK_LPD_LSBUS, PM_DEV_TTC_1),
-    PM_CLOCK2NODE(PM_CLOCK_LPD_LSBUS, PM_DEV_TTC_2),
-    PM_CLOCK2NODE(PM_CLOCK_LPD_LSBUS, PM_DEV_TTC_3),
-    PM_CLOCK2NODE(PM_CLOCK_USB0_BUS_REF, PM_DEV_USB_0),
-    PM_CLOCK2NODE(PM_CLOCK_USB1_BUS_REF, PM_DEV_USB_1),
-    PM_CLOCK2NODE(PM_CLOCK_USB3_DUAL_REF, PM_DEV_USB_0),
-    PM_CLOCK2NODE(PM_CLOCK_USB3_DUAL_REF, PM_DEV_USB_1),
-    PM_CLOCK2NODE(PM_CLOCK_CPU_R5, PM_DEV_RPU),
-    PM_CLOCK2NODE(PM_CLOCK_CPU_R5_CORE, PM_DEV_RPU),
-    PM_CLOCK2NODE(PM_CLOCK_CSU_PLL, PM_DEV_PCAP),
-    PM_CLOCK2NODE(PM_CLOCK_PCAP, PM_DEV_PCAP),
-    PM_CLOCK2NODE(PM_CLOCK_GEM_TSU_REF, PM_DEV_ETH_0),
-    PM_CLOCK2NODE(PM_CLOCK_GEM_TSU_REF, PM_DEV_ETH_1),
-    PM_CLOCK2NODE(PM_CLOCK_GEM_TSU_REF, PM_DEV_ETH_2),
-    PM_CLOCK2NODE(PM_CLOCK_GEM_TSU_REF, PM_DEV_ETH_3),
-    PM_CLOCK2NODE(PM_CLOCK_GEM_TSU, PM_DEV_ETH_0),
-    PM_CLOCK2NODE(PM_CLOCK_GEM_TSU, PM_DEV_ETH_1),
-    PM_CLOCK2NODE(PM_CLOCK_GEM_TSU, PM_DEV_ETH_2),
-    PM_CLOCK2NODE(PM_CLOCK_GEM_TSU, PM_DEV_ETH_3),
-    PM_CLOCK2NODE(PM_CLOCK_GEM0_TX, PM_DEV_ETH_0),
-    PM_CLOCK2NODE(PM_CLOCK_GEM1_TX, PM_DEV_ETH_1),
-    PM_CLOCK2NODE(PM_CLOCK_GEM2_TX, PM_DEV_ETH_2),
-    PM_CLOCK2NODE(PM_CLOCK_GEM3_TX, PM_DEV_ETH_3),
-    PM_CLOCK2NODE(PM_CLOCK_GEM0_RX, PM_DEV_ETH_0),
-    PM_CLOCK2NODE(PM_CLOCK_GEM1_RX, PM_DEV_ETH_1),
-    PM_CLOCK2NODE(PM_CLOCK_GEM2_RX, PM_DEV_ETH_2),
-    PM_CLOCK2NODE(PM_CLOCK_GEM3_RX, PM_DEV_ETH_3),
-    PM_CLOCK2NODE(PM_CLOCK_QSPI_REF, PM_DEV_QSPI),
-    PM_CLOCK2NODE(PM_CLOCK_SDIO0_REF, PM_DEV_SD_0),
-    PM_CLOCK2NODE(PM_CLOCK_SDIO1_REF, PM_DEV_SD_1),
-    PM_CLOCK2NODE(PM_CLOCK_UART0_REF, PM_DEV_UART_0),
-    PM_CLOCK2NODE(PM_CLOCK_UART1_REF, PM_DEV_UART_1),
-    PM_CLOCK2NODE(PM_CLOCK_SPI0_REF, PM_DEV_SPI_0),
-    PM_CLOCK2NODE(PM_CLOCK_SPI1_REF, PM_DEV_SPI_1),
-    PM_CLOCK2NODE(PM_CLOCK_NAND_REF, PM_DEV_NAND),
-    PM_CLOCK2NODE(PM_CLOCK_I2C0_REF, PM_DEV_I2C_0),
-    PM_CLOCK2NODE(PM_CLOCK_I2C1_REF, PM_DEV_I2C_1),
-    PM_CLOCK2NODE(PM_CLOCK_CAN0_REF, PM_DEV_CAN_0),
-    PM_CLOCK2NODE(PM_CLOCK_CAN1_REF, PM_DEV_CAN_1),
-    PM_CLOCK2NODE(PM_CLOCK_CAN0, PM_DEV_CAN_0),
-    PM_CLOCK2NODE(PM_CLOCK_CAN1, PM_DEV_CAN_1),
-    PM_CLOCK2NODE(PM_CLOCK_DLL_REF, PM_DEV_SD_0),
-    PM_CLOCK2NODE(PM_CLOCK_DLL_REF, PM_DEV_SD_1),
-    PM_CLOCK2NODE(PM_CLOCK_ADMA_REF, PM_DEV_ADMA),
-    PM_CLOCK2NODE(PM_CLOCK_AMS_REF, PM_DEV_LPD),
-    PM_CLOCK2NODE(PM_CLOCK_PL0_REF, PM_DEV_PL),
-    PM_CLOCK2NODE(PM_CLOCK_PL1_REF, PM_DEV_PL),
-    PM_CLOCK2NODE(PM_CLOCK_PL2_REF, PM_DEV_PL),
-    PM_CLOCK2NODE(PM_CLOCK_PL3_REF, PM_DEV_PL),
-    PM_CLOCK2NODE(PM_CLOCK_RPLL_INT, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_RPLL_PRE_SRC, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_RPLL_INT_MUX, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_RPLL_POST_SRC, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_VPLL_INT, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_VPLL_PRE_SRC, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_VPLL_INT_MUX, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_VPLL_POST_SRC, PM_DEV_DP),
-    PM_CLOCK2NODE(PM_CLOCK_CAN0_MIO, PM_DEV_CAN_0),
-    PM_CLOCK2NODE(PM_CLOCK_CAN1_MIO, PM_DEV_CAN_1),
-    PM_CLOCK2NODE(PM_CLOCK_GEM0_REF, PM_DEV_ETH_0),
-    PM_CLOCK2NODE(PM_CLOCK_GEM1_REF, PM_DEV_ETH_1),
-    PM_CLOCK2NODE(PM_CLOCK_GEM2_REF, PM_DEV_ETH_2),
-    PM_CLOCK2NODE(PM_CLOCK_GEM3_REF, PM_DEV_ETH_3),
-    PM_CLOCK2NODE(PM_CLOCK_GEM0_REF_UNGATED, PM_DEV_ETH_0),
-    PM_CLOCK2NODE(PM_CLOCK_GEM1_REF_UNGATED, PM_DEV_ETH_1),
-    PM_CLOCK2NODE(PM_CLOCK_GEM2_REF_UNGATED, PM_DEV_ETH_2),
-    PM_CLOCK2NODE(PM_CLOCK_GEM3_REF_UNGATED, PM_DEV_ETH_3),
+    PM_CLOCK2NODE(PM_CLK_RPLL, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_VPLL, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_RPLL_TO_FPD, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_VPLL_TO_LPD, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_DP_VIDEO_REF, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_DP_AUDIO_REF, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_DP_STC_REF, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_GDMA_REF, PM_DEV_GDMA),
+    PM_CLOCK2NODE(PM_CLK_DPDMA_REF, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_SATA_REF, PM_DEV_SATA),
+    PM_CLOCK2NODE(PM_CLK_PCIE_REF, PM_DEV_PCIE),
+    PM_CLOCK2NODE(PM_CLK_GPU_REF, PM_DEV_GPU),
+    PM_CLOCK2NODE(PM_CLK_GPU_PP0_REF, PM_DEV_GPU),
+    PM_CLOCK2NODE(PM_CLK_GPU_PP1_REF, PM_DEV_GPU),
+    PM_CLOCK2NODE(PM_CLK_TOPSW_LSBUS, PM_DEV_DDR),
+    PM_CLOCK2NODE(PM_CLK_LPD_LSBUS, PM_DEV_TTC_0),
+    PM_CLOCK2NODE(PM_CLK_LPD_LSBUS, PM_DEV_TTC_1),
+    PM_CLOCK2NODE(PM_CLK_LPD_LSBUS, PM_DEV_TTC_2),
+    PM_CLOCK2NODE(PM_CLK_LPD_LSBUS, PM_DEV_TTC_3),
+    PM_CLOCK2NODE(PM_CLK_USB0_BUS_REF, PM_DEV_USB_0),
+    PM_CLOCK2NODE(PM_CLK_USB1_BUS_REF, PM_DEV_USB_1),
+    PM_CLOCK2NODE(PM_CLK_USB3_DUAL_REF, PM_DEV_USB_0),
+    PM_CLOCK2NODE(PM_CLK_USB3_DUAL_REF, PM_DEV_USB_1),
+    PM_CLOCK2NODE(PM_CLK_CPU_R5, PM_DEV_RPU),
+    PM_CLOCK2NODE(PM_CLK_CPU_R5_CORE, PM_DEV_RPU),
+    PM_CLOCK2NODE(PM_CLK_CSU_PLL, PM_DEV_PCAP),
+    PM_CLOCK2NODE(PM_CLK_PCAP, PM_DEV_PCAP),
+    PM_CLOCK2NODE(PM_CLK_GEM_TSU_REF, PM_DEV_ETH_0),
+    PM_CLOCK2NODE(PM_CLK_GEM_TSU_REF, PM_DEV_ETH_1),
+    PM_CLOCK2NODE(PM_CLK_GEM_TSU_REF, PM_DEV_ETH_2),
+    PM_CLOCK2NODE(PM_CLK_GEM_TSU_REF, PM_DEV_ETH_3),
+    PM_CLOCK2NODE(PM_CLK_GEM_TSU, PM_DEV_ETH_0),
+    PM_CLOCK2NODE(PM_CLK_GEM_TSU, PM_DEV_ETH_1),
+    PM_CLOCK2NODE(PM_CLK_GEM_TSU, PM_DEV_ETH_2),
+    PM_CLOCK2NODE(PM_CLK_GEM_TSU, PM_DEV_ETH_3),
+    PM_CLOCK2NODE(PM_CLK_GEM0_TX, PM_DEV_ETH_0),
+    PM_CLOCK2NODE(PM_CLK_GEM1_TX, PM_DEV_ETH_1),
+    PM_CLOCK2NODE(PM_CLK_GEM2_TX, PM_DEV_ETH_2),
+    PM_CLOCK2NODE(PM_CLK_GEM3_TX, PM_DEV_ETH_3),
+    PM_CLOCK2NODE(PM_CLK_GEM0_RX, PM_DEV_ETH_0),
+    PM_CLOCK2NODE(PM_CLK_GEM1_RX, PM_DEV_ETH_1),
+    PM_CLOCK2NODE(PM_CLK_GEM2_RX, PM_DEV_ETH_2),
+    PM_CLOCK2NODE(PM_CLK_GEM3_RX, PM_DEV_ETH_3),
+    PM_CLOCK2NODE(PM_CLK_QSPI_REF, PM_DEV_QSPI),
+    PM_CLOCK2NODE(PM_CLK_SDIO0_REF, PM_DEV_SD_0),
+    PM_CLOCK2NODE(PM_CLK_SDIO1_REF, PM_DEV_SD_1),
+    PM_CLOCK2NODE(PM_CLK_UART0_REF, PM_DEV_UART_0),
+    PM_CLOCK2NODE(PM_CLK_UART1_REF, PM_DEV_UART_1),
+    PM_CLOCK2NODE(PM_CLK_SPI0_REF, PM_DEV_SPI_0),
+    PM_CLOCK2NODE(PM_CLK_SPI1_REF, PM_DEV_SPI_1),
+    PM_CLOCK2NODE(PM_CLK_NAND_REF, PM_DEV_NAND),
+    PM_CLOCK2NODE(PM_CLK_I2C0_REF, PM_DEV_I2C_0),
+    PM_CLOCK2NODE(PM_CLK_I2C1_REF, PM_DEV_I2C_1),
+    PM_CLOCK2NODE(PM_CLK_CAN0_REF, PM_DEV_CAN_0),
+    PM_CLOCK2NODE(PM_CLK_CAN1_REF, PM_DEV_CAN_1),
+    PM_CLOCK2NODE(PM_CLK_CAN0, PM_DEV_CAN_0),
+    PM_CLOCK2NODE(PM_CLK_CAN1, PM_DEV_CAN_1),
+    PM_CLOCK2NODE(PM_CLK_DLL_REF, PM_DEV_SD_0),
+    PM_CLOCK2NODE(PM_CLK_DLL_REF, PM_DEV_SD_1),
+    PM_CLOCK2NODE(PM_CLK_ADMA_REF, PM_DEV_ADMA),
+    PM_CLOCK2NODE(PM_CLK_AMS_REF, PM_DEV_LPD),
+    PM_CLOCK2NODE(PM_CLK_PL0_REF, PM_DEV_PL),
+    PM_CLOCK2NODE(PM_CLK_PL1_REF, PM_DEV_PL),
+    PM_CLOCK2NODE(PM_CLK_PL2_REF, PM_DEV_PL),
+    PM_CLOCK2NODE(PM_CLK_PL3_REF, PM_DEV_PL),
+    PM_CLOCK2NODE(PM_CLK_RPLL_INT, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_RPLL_PRE_SRC, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_RPLL_INT_MUX, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_RPLL_POST_SRC, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_VPLL_INT, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_VPLL_PRE_SRC, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_VPLL_INT_MUX, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_VPLL_POST_SRC, PM_DEV_DP),
+    PM_CLOCK2NODE(PM_CLK_CAN0_MIO, PM_DEV_CAN_0),
+    PM_CLOCK2NODE(PM_CLK_CAN1_MIO, PM_DEV_CAN_1),
+    PM_CLOCK2NODE(PM_CLK_GEM0_REF, PM_DEV_ETH_0),
+    PM_CLOCK2NODE(PM_CLK_GEM1_REF, PM_DEV_ETH_1),
+    PM_CLOCK2NODE(PM_CLK_GEM2_REF, PM_DEV_ETH_2),
+    PM_CLOCK2NODE(PM_CLK_GEM3_REF, PM_DEV_ETH_3),
+    PM_CLOCK2NODE(PM_CLK_GEM0_REF_UNGATED, PM_DEV_ETH_0),
+    PM_CLOCK2NODE(PM_CLK_GEM1_REF_UNGATED, PM_DEV_ETH_1),
+    PM_CLOCK2NODE(PM_CLK_GEM2_REF_UNGATED, PM_DEV_ETH_2),
+    PM_CLOCK2NODE(PM_CLK_GEM3_REF_UNGATED, PM_DEV_ETH_3),
 };
 
 static bool pm_check_access(const struct pm_access *acl, struct domain *d, int idx)
@@ -565,7 +565,7 @@ static bool domain_has_reset_access(struct domain *d, enum pm_reset rst)
 /* Check if a clock id is valid */
 static bool clock_id_is_valid(enum pm_clock clk_id)
 {
-    if ( clk_id < 0 || clk_id >= PM_CLOCK_END )
+    if ( clk_id < 0 || clk_id >= PM_CLK_END )
         return false;
 
     return true;

diff --git a/xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h b/xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h
index b19c4a9d470107e6c05f1cd104e0926d437f36b6..ea913474d61f24b810e8fb2c7bb28eeb6206c23f 100644 (file)
--- a/xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h
+++ b/xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h
@@ -329,119 +329,119 @@ enum pm_reset {
 };
 
 enum pm_clock {
-    PM_CLOCK_IOPLL,
-    PM_CLOCK_RPLL,
-    PM_CLOCK_APLL,
-    PM_CLOCK_DPLL,
-    PM_CLOCK_VPLL,
-    PM_CLOCK_IOPLL_TO_FPD,
-    PM_CLOCK_RPLL_TO_FPD,
-    PM_CLOCK_APLL_TO_LPD,
-    PM_CLOCK_DPLL_TO_LPD,
-    PM_CLOCK_VPLL_TO_LPD,
-    PM_CLOCK_ACPU,
-    PM_CLOCK_ACPU_HALF,
-    PM_CLOCK_DBG_FPD,
-    PM_CLOCK_DBG_LPD,
-    PM_CLOCK_DBG_TRACE,
-    PM_CLOCK_DBG_TSTMP,
-    PM_CLOCK_DP_VIDEO_REF,
-    PM_CLOCK_DP_AUDIO_REF,
-    PM_CLOCK_DP_STC_REF,
-    PM_CLOCK_GDMA_REF,
-    PM_CLOCK_DPDMA_REF,
-    PM_CLOCK_DDR_REF,
-    PM_CLOCK_SATA_REF,
-    PM_CLOCK_PCIE_REF,
-    PM_CLOCK_GPU_REF,
-    PM_CLOCK_GPU_PP0_REF,
-    PM_CLOCK_GPU_PP1_REF,
-    PM_CLOCK_TOPSW_MAIN,
-    PM_CLOCK_TOPSW_LSBUS,
-    PM_CLOCK_GTGREF0_REF,
-    PM_CLOCK_LPD_SWITCH,
-    PM_CLOCK_LPD_LSBUS,
-    PM_CLOCK_USB0_BUS_REF,
-    PM_CLOCK_USB1_BUS_REF,
-    PM_CLOCK_USB3_DUAL_REF,
-    PM_CLOCK_USB0,
-    PM_CLOCK_USB1,
-    PM_CLOCK_CPU_R5,
-    PM_CLOCK_CPU_R5_CORE,
-    PM_CLOCK_CSU_SPB,
-    PM_CLOCK_CSU_PLL,
-    PM_CLOCK_PCAP,
-    PM_CLOCK_IOU_SWITCH,
-    PM_CLOCK_GEM_TSU_REF,
-    PM_CLOCK_GEM_TSU,
-    PM_CLOCK_GEM0_TX,
-    PM_CLOCK_GEM1_TX,
-    PM_CLOCK_GEM2_TX,
-    PM_CLOCK_GEM3_TX,
-    PM_CLOCK_GEM0_RX,
-    PM_CLOCK_GEM1_RX,
-    PM_CLOCK_GEM2_RX,
-    PM_CLOCK_GEM3_RX,
-    PM_CLOCK_QSPI_REF,
-    PM_CLOCK_SDIO0_REF,
-    PM_CLOCK_SDIO1_REF,
-    PM_CLOCK_UART0_REF,
-    PM_CLOCK_UART1_REF,
-    PM_CLOCK_SPI0_REF,
-    PM_CLOCK_SPI1_REF,
-    PM_CLOCK_NAND_REF,
-    PM_CLOCK_I2C0_REF,
-    PM_CLOCK_I2C1_REF,
-    PM_CLOCK_CAN0_REF,
-    PM_CLOCK_CAN1_REF,
-    PM_CLOCK_CAN0,
-    PM_CLOCK_CAN1,
-    PM_CLOCK_DLL_REF,
-    PM_CLOCK_ADMA_REF,
-    PM_CLOCK_TIMESTAMP_REF,
-    PM_CLOCK_AMS_REF,
-    PM_CLOCK_PL0_REF,
-    PM_CLOCK_PL1_REF,
-    PM_CLOCK_PL2_REF,
-    PM_CLOCK_PL3_REF,
-    PM_CLOCK_WDT,
-    PM_CLOCK_IOPLL_INT,
-    PM_CLOCK_IOPLL_PRE_SRC,
-    PM_CLOCK_IOPLL_HALF,
-    PM_CLOCK_IOPLL_INT_MUX,
-    PM_CLOCK_IOPLL_POST_SRC,
-    PM_CLOCK_RPLL_INT,
-    PM_CLOCK_RPLL_PRE_SRC,
-    PM_CLOCK_RPLL_HALF,
-    PM_CLOCK_RPLL_INT_MUX,
-    PM_CLOCK_RPLL_POST_SRC,
-    PM_CLOCK_APLL_INT,
-    PM_CLOCK_APLL_PRE_SRC,
-    PM_CLOCK_APLL_HALF,
-    PM_CLOCK_APLL_INT_MUX,
-    PM_CLOCK_APLL_POST_SRC,
-    PM_CLOCK_DPLL_INT,
-    PM_CLOCK_DPLL_PRE_SRC,
-    PM_CLOCK_DPLL_HALF,
-    PM_CLOCK_DPLL_INT_MUX,
-    PM_CLOCK_DPLL_POST_SRC,
-    PM_CLOCK_VPLL_INT,
-    PM_CLOCK_VPLL_PRE_SRC,
-    PM_CLOCK_VPLL_HALF,
-    PM_CLOCK_VPLL_INT_MUX,
-    PM_CLOCK_VPLL_POST_SRC,
-    PM_CLOCK_CAN0_MIO,
-    PM_CLOCK_CAN1_MIO,
-    PM_CLOCK_ACPU_FULL,
-    PM_CLOCK_GEM0_REF,
-    PM_CLOCK_GEM1_REF,
-    PM_CLOCK_GEM2_REF,
-    PM_CLOCK_GEM3_REF,
-    PM_CLOCK_GEM0_REF_UNGATED,
-    PM_CLOCK_GEM1_REF_UNGATED,
-    PM_CLOCK_GEM2_REF_UNGATED,
-    PM_CLOCK_GEM3_REF_UNGATED,
-    PM_CLOCK_END,
+    PM_CLK_IOPLL,
+    PM_CLK_RPLL,
+    PM_CLK_APLL,
+    PM_CLK_DPLL,
+    PM_CLK_VPLL,
+    PM_CLK_IOPLL_TO_FPD,
+    PM_CLK_RPLL_TO_FPD,
+    PM_CLK_APLL_TO_LPD,
+    PM_CLK_DPLL_TO_LPD,
+    PM_CLK_VPLL_TO_LPD,
+    PM_CLK_ACPU,
+    PM_CLK_ACPU_HALF,
+    PM_CLK_DBG_FPD,
+    PM_CLK_DBG_LPD,
+    PM_CLK_DBG_TRACE,
+    PM_CLK_DBG_TSTMP,
+    PM_CLK_DP_VIDEO_REF,
+    PM_CLK_DP_AUDIO_REF,
+    PM_CLK_DP_STC_REF,
+    PM_CLK_GDMA_REF,
+    PM_CLK_DPDMA_REF,
+    PM_CLK_DDR_REF,
+    PM_CLK_SATA_REF,
+    PM_CLK_PCIE_REF,
+    PM_CLK_GPU_REF,
+    PM_CLK_GPU_PP0_REF,
+    PM_CLK_GPU_PP1_REF,
+    PM_CLK_TOPSW_MAIN,
+    PM_CLK_TOPSW_LSBUS,
+    PM_CLK_GTGREF0_REF,
+    PM_CLK_LPD_SWITCH,
+    PM_CLK_LPD_LSBUS,
+    PM_CLK_USB0_BUS_REF,
+    PM_CLK_USB1_BUS_REF,
+    PM_CLK_USB3_DUAL_REF,
+    PM_CLK_USB0,
+    PM_CLK_USB1,
+    PM_CLK_CPU_R5,
+    PM_CLK_CPU_R5_CORE,
+    PM_CLK_CSU_SPB,
+    PM_CLK_CSU_PLL,
+    PM_CLK_PCAP,
+    PM_CLK_IOU_SWITCH,
+    PM_CLK_GEM_TSU_REF,
+    PM_CLK_GEM_TSU,
+    PM_CLK_GEM0_TX,
+    PM_CLK_GEM1_TX,
+    PM_CLK_GEM2_TX,
+    PM_CLK_GEM3_TX,
+    PM_CLK_GEM0_RX,
+    PM_CLK_GEM1_RX,
+    PM_CLK_GEM2_RX,
+    PM_CLK_GEM3_RX,
+    PM_CLK_QSPI_REF,
+    PM_CLK_SDIO0_REF,
+    PM_CLK_SDIO1_REF,
+    PM_CLK_UART0_REF,
+    PM_CLK_UART1_REF,
+    PM_CLK_SPI0_REF,
+    PM_CLK_SPI1_REF,
+    PM_CLK_NAND_REF,
+    PM_CLK_I2C0_REF,
+    PM_CLK_I2C1_REF,
+    PM_CLK_CAN0_REF,
+    PM_CLK_CAN1_REF,
+    PM_CLK_CAN0,
+    PM_CLK_CAN1,
+    PM_CLK_DLL_REF,
+    PM_CLK_ADMA_REF,
+    PM_CLK_TIMESTAMP_REF,
+    PM_CLK_AMS_REF,
+    PM_CLK_PL0_REF,
+    PM_CLK_PL1_REF,
+    PM_CLK_PL2_REF,
+    PM_CLK_PL3_REF,
+    PM_CLK_WDT,
+    PM_CLK_IOPLL_INT,
+    PM_CLK_IOPLL_PRE_SRC,
+    PM_CLK_IOPLL_HALF,
+    PM_CLK_IOPLL_INT_MUX,
+    PM_CLK_IOPLL_POST_SRC,
+    PM_CLK_RPLL_INT,
+    PM_CLK_RPLL_PRE_SRC,
+    PM_CLK_RPLL_HALF,
+    PM_CLK_RPLL_INT_MUX,
+    PM_CLK_RPLL_POST_SRC,
+    PM_CLK_APLL_INT,
+    PM_CLK_APLL_PRE_SRC,
+    PM_CLK_APLL_HALF,
+    PM_CLK_APLL_INT_MUX,
+    PM_CLK_APLL_POST_SRC,
+    PM_CLK_DPLL_INT,
+    PM_CLK_DPLL_PRE_SRC,
+    PM_CLK_DPLL_HALF,
+    PM_CLK_DPLL_INT_MUX,
+    PM_CLK_DPLL_POST_SRC,
+    PM_CLK_VPLL_INT,
+    PM_CLK_VPLL_PRE_SRC,
+    PM_CLK_VPLL_HALF,
+    PM_CLK_VPLL_INT_MUX,
+    PM_CLK_VPLL_POST_SRC,
+    PM_CLK_CAN0_MIO,
+    PM_CLK_CAN1_MIO,
+    PM_CLK_ACPU_FULL,
+    PM_CLK_GEM0_REF,
+    PM_CLK_GEM1_REF,
+    PM_CLK_GEM2_REF,
+    PM_CLK_GEM3_REF,
+    PM_CLK_GEM0_REF_UNGATED,
+    PM_CLK_GEM1_REF_UNGATED,
+    PM_CLK_GEM2_REF_UNGATED,
+    PM_CLK_GEM3_REF_UNGATED,
+    PM_CLK_END,
 };
 
 extern bool zynqmp_eemi(struct cpu_user_regs *regs);