Avoids some particularly obscure magic numbers.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
* This update is safe from a security point of view, as this pcpu
* is never going to try to sysret back to a PV vcpu.
*/
- _set_gate_lower(&idt_tables[i][TRAP_nmi], 14, 0, &trap_nop);
+ _set_gate_lower(&idt_tables[i][TRAP_nmi],
+ SYS_DESC_irq_gate, 0, &trap_nop);
set_ist(&idt_tables[i][TRAP_machine_check], IST_NONE);
}
else
/* Keep secondary tables in sync with IRQ updates. */
for ( i = 1; i < nr_cpu_ids; i++ )
if ( idt_tables[i] != NULL )
- _set_gate(&idt_tables[i][n], 14, dpl, addr);
- _set_gate(&idt_table[n], 14, dpl, addr);
+ _set_gate(&idt_tables[i][n], SYS_DESC_irq_gate, dpl, addr);
+ _set_gate(&idt_table[n], SYS_DESC_irq_gate, dpl, addr);
}
static void set_swint_gate(unsigned int n, void *addr)
this_cpu(gdt_table) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY,
(unsigned long)tss,
offsetof(struct tss_struct, __cacheline_filler) - 1,
- 9);
+ SYS_DESC_tss_avail);
_set_tssldt_desc(
this_cpu(compat_gdt_table) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY,
(unsigned long)tss,
offsetof(struct tss_struct, __cacheline_filler) - 1,
- 11);
+ SYS_DESC_tss_busy);
/* Switch to non-compat GDT (which has B bit clear) to execute LTR. */
asm volatile (
set_ist(&idt_table[TRAP_nmi], IST_NMI);
set_ist(&idt_table[TRAP_machine_check], IST_MCE);
- /*
- * The 32-on-64 hypercall entry vector is only accessible from ring 1.
- * Also note that this is a trap gate, not an interrupt gate.
- */
- _set_gate(idt_table+HYPERCALL_VECTOR, 15, 1, &compat_hypercall);
+ /* The 32-on-64 hypercall vector is only accessible from ring 1. */
+ _set_gate(idt_table + HYPERCALL_VECTOR,
+ SYS_DESC_trap_gate, 1, &compat_hypercall);
/* Fast trap for int80 (faster than taking the #GP-fixup path). */
- _set_gate(idt_table+0x80, 15, 3, &int80_direct_trap);
+ _set_gate(idt_table + 0x80, SYS_DESC_trap_gate, 3, &int80_direct_trap);
}
stack_bottom = (char *)get_stack_bottom();
#ifndef __ASSEMBLY__
+/* System Descriptor types for GDT and IDT entries. */
+#define SYS_DESC_ldt 2
+#define SYS_DESC_tss_avail 9
+#define SYS_DESC_tss_busy 11
+#define SYS_DESC_call_gate 12
+#define SYS_DESC_irq_gate 14
+#define SYS_DESC_trap_gate 15
+
struct desc_struct {
u32 a, b;
};
desc = (!is_pv_32on64_vcpu(v)
? this_cpu(gdt_table) : this_cpu(compat_gdt_table))
+ LDT_ENTRY - FIRST_RESERVED_GDT_ENTRY;
- _set_tssldt_desc(desc, LDT_VIRT_START(v), ents*8-1, 2);
+ _set_tssldt_desc(desc, LDT_VIRT_START(v), ents*8-1, SYS_DESC_ldt);
__asm__ __volatile__ ( "lldt %%ax" : : "a" (LDT_ENTRY << 3) );
}
}